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PCA9535ECMTTXG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
PCA9535E, PCA9535EC
www.onsemi.com
10
Registers 4 and 5: Polarity Inversion Registers
These registers allow the polarity of the data in the input
port registers to be inverted. The input port data polarity will
be inverted when its corresponding bit in these registers is
set (written with ‘1’), and retained when the bit is cleared
(written with a ‘0’).
Table 12. POLARITY INVERSION PORT 0 REGISTER
Bit 7 6 5 4 3 2 1 0
Symbol N0.7 N0.6 N0.5 N0.4 N0.3 N0.2 N0.1 N0.0
Default 0 0 0 0 0 0 0 0
Table 13. POLARITY INVERSION PORT 1 REGISTER
Bit 7 6 5 4 3 2 1 0
Symbol N1.7 N1.6 N1.5 N1.4 N1.3 N1.2 N1.1 N1.0
Default 0 0 0 0 0 0 0 0
Registers 6 and 7: Configuration Registers
The I/O pin directions are configured through the
configuration registers. When a bit in the configuration
registers is set (written with ‘1’), the bit’s corresponding port
pin is enabled as an input with the output driver in
high−impedance. When a bit is cleared (written with ‘0’),
the corresponding port pin is enabled as an output. At reset,
the device’s ports are inputs.
Table 14. CONFIGURATION PORT 0 REGISTER
Bit 7 6 5 4 3 2 1 0
Symbol C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 C0.0
Default 1 1 1 1 1 1 1 1
Table 15. CONFIGURATION PORT 1 REGISTER
Bit 7 6 5 4 3 2 1 0
Symbol C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Default 1 1 1 1 1 1 1 1
Power−on Reset
Upon application of power, an internal Power−On Reset
(POR) holds the PCA9535E/PCA9535EC in a reset
condition while V
DD
is ramping up. When V
DD
has reached
V
POR
, the reset condition is released and the
PCA9535E/PCA9535EC registers and SMBus state
machine will initialize to their default states. The reset is
typically completed by the POR and the part enabled by the
time the power supply is above V
POR
. However, when doing
a power reset cycle, it is necessary to lower the power supply
below 0.2 V, and then restored to the operating voltage.
Please refer to application note AND9169/D for
recommended power−up and power−cycle reset profiles.
I/O Port (See Figure 2)
When an I/O pin is configured as an input on the
PCA9535E, FETs Q1 and Q2 are off, creating a
high−impedance input. The input voltage may be raised
above V
DD
to a maximum of 5.5 V. In the case of
PCA9535EC, FET Q1 has been removed and the
open−drain FET Q2 will function the same as PCA9535E.
When the I/O pin is configured as an output on the
PCA9535E, then either Q1 or Q2 is enabled, depending on
the state of the output port register. With the PCA9535EC,
an external pullup is required to pull the I/O pin HIGH when
its corresponding output port register bit is a 1. Care should
be exercised if an external voltage is applied to an I/O
configured as an output because of the low−impedance path
that exists between the pin and either V
DD
or V
SS
.
PCA9535E, PCA9535EC
www.onsemi.com
11
BUS TRANSACTIONS
Writing to the Port Registers
To transmit data to the PCA9535E/PCA9535EC, the bus
master must first send the device address with the least
significant bit set to logic 0 (see Figure 5 “PCA9535E and
PCA9535EC device address”). The command byte is sent
after the address and determines which registers will receive
the data following the command byte.
There are eight registers within the
PCA9535E/PCA9535EC. These registers are configured to
operate as four register pairs: Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. Data
bytes are sent alternately to each register in a register pair
(see Figures 6 and 7). For example, if one byte is sent to
Output Port 1 (register 3), then the next byte will be stored
in Output Port 0 (register 2). There is no limitation on the
number of data bytes sent in one write transmission. In this
way, each 8−bit register may be updated independently of
the other registers.
Figure 6. Write to Output Port Registers
A2 A1 A0 0 AS A6
START condition R/W acknowledge
from slave
A
SCL
SDA A
write to port
data out
from port 0
P
t
v(Q)
987654321
command byte data to port 0
DATA 0
slave address
0
STOP
condition
0.0
0.7
acknowledge
from slave
acknowledge
from slave
data to port 1
DATA 1 1.0
1.7 A
data out
from port 1
t
v(Q)
DATA VALID
A5 A4 A3 0 0 0 0 0 1 0
Figure 7. Write to Configuration Registers
A2 A1 A0 0 AS A6
START condition
R/W
acknowledge
from slave
A
SCL
SDA AP
98765432
1
command byte
data to register
DATA 0
slave address
0
STOP
condition
LSB
MSB
acknowledge
from slave
acknowledge
from slave
data to register
DATA 1
LSB
MSB
AA5 A4 A3 0 0 0 1 1 00
Reading the Port Registers
To read data from the PCA9535E/PCA9535EC, the bus
master must first send the PCA9535E/PCA9535EC address
with the least significant bit set to logic 0 (see Figure 5
“PCA9535E and PCA9535EC device address”). The
command byte is sent after the address and determines
which register will be accessed.
After a restart, the device address must be sent again, but
this time, the least significant bit is set to logic 1. Data from
the register defined by the command byte will then be sent
by the PCA9535E/PCA9535EC (see Figures 8, 9 and 10).
Data is clocked into the register on the falling edge of the
acknowledge clock pulse. After the first byte is read,
additional bytes may be read but with data alternately
coming from each register in the pair. For example, if you
read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data
bytes received in one read transmission but the bus master
must not acknowledge the data for the final byte received.
PCA9535E, PCA9535EC
www.onsemi.com
12
Figure 8. Read from Register
Remark: Transfer can be stopped at any time by a STOP condition.
AS
START condition R/W
acknowledge
from slave
A
acknowledge
from slave
SDA
AP
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
A2 A1 A0
1AA6
R/W
acknowledge
from slave
slave address
at this moment master−transmitter becomes master−receiver
and slave−receiver becomes slave−transmitter
NA
no acknowledge
from master
COMMAND BYTE
A2 A1 A0A6 0
data from lower or
upper byte of register
LSB
MSB
DATA (last byte)
data from upper or
lower byte of register
LSB
MSB
A5 A4 A3
A5 A4 A3
Figure 9. Read from Input Port Register, Scenario 1
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
A2 A1 A0 1 AS A6
START condition R/W
acknowledge
from slave
A
SCL
SDA A
read from port 0
P
98765432
1
I0.xslave address
7
STOP condition
acknowledge
from master
A
I1.x
7
acknowledge
from master
A
I0.x
7
acknowledge
from master
1
I1.x
7
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
t
v(INT_N)
t
rst(INT_N)
A5A4A3 6543210 6543210 6543210 6543210
Figure 10. Read from Input Port Register, Scenario 2
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
A2 A1 A0 1 AS A6
START condition
R/W
acknowledge
from slave
A
SCL
SDA A
read from port 0
P
98765432
1
I0.xslave address
STOP condition
acknowledge
from master
A
I1.x
acknowledge
from master
A
I0.x
acknowledge
from master
1
I1.x
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
t
v(INT_N)
t
rst(INT_N)
21ATAD30ATAD01ATAD00ATAD
DATA 00 DATA 01
t
h(D)
t
h(D)
DATA 02
t
su(D)
DATA 03
t
su(D)
21ATAD11ATAD01ATAD
A5A4 A3
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

PCA9535ECMTTXG

Mfr. #:
Buy PCA9535ECMTTXG
Manufacturer:
ON Semiconductor
Description:
Interface - I/O Expanders 16-BIT I/O EXPANDER
Lifecycle:
New from this manufacturer.
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