PCA9535ECMTTXG Datasheet PCA9535EDTR2G, NLVPCA9535EDTR2G, PCA9535ECDWR2G | P13-P15

PCA9535E, PCA9535EC

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Interrupt Output

The open−drain interrupt output is activated when an I/O

pin configured as an input changes state. The interrupt is

deactivated when the input pin returns to its previous state

or when the Input Port register is read (see Figure 9). A pin

configured as an output cannot cause an interrupt. Since

each 8−bit port is read independently, the interrupt caused by

Port 0 will not be cleared by a read of Port 1 or the other way

around.

Remark: Changing an I/O from an output to an input may

cause a false interrupt to occur if the state of the pin does not

match the contents of the Input Port register.

APPLICATION INFORMATION

Figure 11. Typical Application

Device address configured as 0100 000xb for this example.

IO0_0, IO0_2, IO0_3 configured as outputs.

IO0_1, IO0_4, IO0_5 configured as inputs.

IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs.

PCA9535E

IO0_0

IO0_1

SCL

SDA

(5 V)

MASTER

CONTROLLER

INT

IO0_2

AD2

AD1

AD0

GND

INT

10 kW

SUB−SYSTEM 1

(e.g., temp

sensor)

IO0_3

INT

SUB−SYSTEM 2

(e.g.,

counter)

RESET

controlled

switch

(e.g.,

7SB or FST)

ENABLE

SUB−SYSTEM 3

(e.g., alarm

system)

ALARM

IO0_4

IO0_5

IO0_6

DIGIT

NUMERIC

KEYPAD

10 kW10 kW 2 kW

IO0_7

IO1_0

IO1_1

IO1_2

IO1_3

IO1_4

IO1_5

IO1_6

IO1_7

SDA

SCL

100 kW

(x3)

Minimizing I

When the I/Os are Used to Control

LEDs

To use the PCA9535E I/Os to control LEDs, the I/Os are

normally connected to V

through a resistor as shown in

Figure 11. The LED acts as a diode. When the LED is off,

the I/O V

is about 1.2 V less than V

. The supply current,

, increases as V

becomes lower than V

For applications requiring low current consumption, such

as battery power applications, it is recommended that the I/O

pin voltages be greater than or equal to V

when the LED

is off. This would minimize current consumption. Figure 12

shows a high value resistor in parallel with the LED.

Figure 13 shows V

less than the LED supply voltage by

at least 1.2 V. Both of these methods maintain the I/O V

or above V

and prevents additional supply current

consumption when the LED is off.

This concern does not occur for the PCA9535EC because

the PCA9535EC I/O pins are open−drain.

PCA9535E, PCA9535EC

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Figure 12. High Value Resistor in Parallel

with the LED

Figure 13. Device Supplied by a Lower Voltage

LED

LEDn

100 kW

LED

LEDn

3.3 V

5 V

Characteristics of the I

C−bus

The I

C−bus is meant for 2−way, 2−line communication

between different ICs or modules. The two lines are the

serial data line (SDA) and the serial clock line (SCL). Both

lines must be connected to a positive supply via a pull−up

resistor when connected to the output stages of a device.

Data transfer may only be initiated when the bus is not busy.

Bit transfer

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during the HIGH

period of the clock pulse. Changes in the data line during the

HIGH period of the clock pulse will be interpreted as control

signals (see Figure 14).

Figure 14. Bit Transfer

data line

stable;

data valid

change

of data

allowed

SDA

SCL

START and STOP conditions

Both data and clock lines remain HIGH when the bus is

not busy. A START condition (S) occurs when there is a

HIGH−to−LOW transition of the data line while the clock is

HIGH. A STOP condition (P) occurs when there is a

LOW−to−HIGH transition of the data line while the clock is

HIGH (see Figure 15).

Figure 15. Definition of START and STOP Conditions

SDA

SCL

STOP condition

SDA

SCL

START condition

PCA9535E, PCA9535EC

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System Configuration

A device generating a message is a ‘transmitter’; a device

receiving is the ‘receiver’. The device that controls the

message is the ‘master’ and the devices which are controlled

by the master are the ‘slaves’ (see Figure 16).

Figure 16. System Configuration

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

C−BUS

MULTIPLEXER

SLAVE

Acknowledge

The number of data bytes transferred between the START

and the STOP conditions from transmitter to receiver is not

limited. Each 8−bit byte is followed by one acknowledge bit.

The acknowledge bit is a HIGH level put on the bus by the

transmitter, whereas the master generates an extra clock

pulse for the acknowledge bit.

A slave receiver which is addressed must generate an

acknowledge after the reception of each byte. Also a master

must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter. The

device that acknowledges has to pull down the SDA line

during the acknowledge clock pulse, such that the SDA line

is stable LOW during the HIGH period of the acknowledge

clock pulse; set−up time and hold time must be taken into

account.

A master receiver signals an end of data to the transmitter

by not generating an acknowledge on the last byte that has

been clocked out of the slave. In this event, the transmitter

must leave the data line HIGH to enable the master to

generate a STOP condition.

Figure 17. Acknowledgement of the I

C Bus

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Timing and Test Setup

Figure 18. Definition of Timing on the I

C Bus

BUF

HD;STA

PP S

LOW

HD;DAT

HIGH

SU;DAT

SU;STA

HD;STA

SU;STO

SDA

SCL

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

PCA9535ECMTTXG

Mfr. #:

Buy PCA9535ECMTTXG

Manufacturer:

ON Semiconductor

Description:

Interface - I/O Expanders 16-BIT I/O EXPANDER

Lifecycle:

New from this manufacturer.

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PCA9535ECMTTXG

PCA9535ECMTTXG

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