PCA9535E, PCA9535EC
www.onsemi.com
6
Table 5. AC ELECTRICAL CHARACTERISTICS V
DD
= 1.65 V to 5.5 V; T
A
= −55°C to +125°C, unless otherwise specified.
Symbol
Parameter
Standard Mode Fast Mode Fast Mode +
Unit
Min Max Min Max Min Max
f
SCL
SCL Clock Frequency 0 0.1 0 0.4 0 1.0 MHz
t
BUF
Bus−Free Time between a STOP and START
Condition
4.7 1.3 0.5
ms
t
HD:STA
Hold Time (Repeated) START Condition 4.0 0.6 0.26
ms
t
SU:STA
Setup Time for a Repeated START Condition 4.7 0.6 0.26
ms
t
SU:STO
Setup Time for STOP Condition 4.0 0.6 0.26
ms
t
HD:DAT
Data Hold Time 0 0 0 ns
t
VD:ACK
Data Valid Acknowledge Time (Note 10) 0.3 3.45 0.1 0.9 0.05 0.45
ms
t
VD:DAT
Data Valid Time (Note 11) 300 50 50 450 ns
t
SU:DAT
Data Setup Time 250 100 50 ns
t
LOW
LOW Period of SCL 4.7 1.3 0.5
ms
t
HIGH
HIGH Period of SCL 4.0 0.6 0.26
ms
t
f
Fall Time of SDA and SCL (Notes 13 and 14) 300 20 +
0.1C
b
(Note 12)
300 120 ns
t
r
Rise Time of SDA and SCL 1000 20 +
0.1C
b
(Note 12)
300 120 ns
t
SP
Pulse Width of Spikes Suppressed by Input
Filter (Note 15)
50 50 50 ns
PORT TIMING: C
L
v 100 pF (See Figures 6, 9 and 10)
t
V(Q)
Data Output Valid Time (V
DD
= 4.5 V to 5.5 V)
(V
DD
= 2.3 V to 4.5 V)
(V
DD
= 1.65 V to 2.3 V)
200
350
550
200
350
550
200
350
550
ns
t
SU(D)
Data Input Setup Time 100 100 100 ns
t
H(D)
Data Input Hold Time 1 1 1
ms
INTERRUPT TIMING: C
L
v 100 pF (See Figures 9 and 10)
t
V(INT_N)
Data Valid Time 4 4 4
ms
t
RST(INT_N)
Reset Delay Time 4 4 4
ms
10.t
VD:ACK
= time for Acknowledgment signal from SCL LOW to SDA (out) LOW.
11. t
VD:DAT
= minimum time for SDA data out to be valid following SCL LOW.
12.C
b
= total capacitance of one bus line in pF.
13.A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to V
IL
of the SCL signal) in order to bridge
the undefined region SCL’s falling edge.
14.The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
f
.
15.Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.