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Table 2. MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DD
DC Supply Voltage −0.5 to +7.0 V
V
I/O
Input / Output Pin Voltage −0.5 to +7.0 V
I
I
Input Current $20 mA
I
O
Output Current $50 mA
I
DD
DC Supply Current $100 mA
I
GND
DC Ground Current $600 mA
P
TOT
Total Power Dissipation 600 mW
P
OUT
Power Dissipation per Output 200 mW
T
STG
Storage Temperature Range −65 to +150 °C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260 °C
T
J
Junction Temperature Under Bias 150 °C
q
JA
Thermal Resistance (Note 1) SOIC−24
TSSOP−24
WQFN24
85
91
68
°C/W
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @
0.125 in
V
ESD
ESD Withstand Voltage Human Body Mode (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 3000
> 400
N/A
V
I
LATCHUP
Latchup Performance Above V
DD
and Below GND at 125°C (Note 5) $100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functional-
ity should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
2. Tested to EIA / JESD22−A114−A.
3. Tested to EIA / JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA / JESD78.
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
DD
Positive DC Supply Voltage 1.65 5.5 V
V
I/O
Switch Input / Output Voltage 0 5.5 V
T
A
Operating Free−Air Temperature −55 +125 °C
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Table 4. DC ELECTRICAL CHARACTERISTICS V
DD
= 1.65 V to 5.5 V, unless otherwise specified.
Symbol
Parameter Conditions
T
A
= −555C to +1255C
Unit
Min Typ Max
SUPPLIES
I
STB
Standby Current (Note 6) Standby mode; no load;
V
I
= 0 V; f
SCL
= 0 Hz; I/O = inputs
V
I
= V
DD
; f
SCL
= 0 Hz; I/O = inputs
39
39
100
100
mA
V
POR
Power−On Reset Voltage (Note 7) 1.5 1.65 V
INPUT SCL; INPUT / OUTPUT SDA
V
IH
High−Level Input Voltage 0.7 x V
DD
V
V
IL
Low−Level Input Voltage 0.3 x V
DD
V
I
OL
Low−Level Output Current V
OL
= 0.4 V; V
DD
< 2.3 V
V
OL
= 0.4 V; V
DD
w 2.3 V
10
20
mA
I
L
Leakage Current V
I
= V
DD
or 0 V $1
mA
C
I
Input Capacitance V
I
= 0 V 4.6 6 pF
I/Os
V
IH
High−Level Input Voltage 0.7 x V
DD
V
V
IL
Low−Level Input Voltage 0.3 x V
DD
V
I
OL
Low−Level Output Current
(Note 8)
V
OL
= 0.5 V; V
DD
= 1.65 V 8 20
mA
V
OL
= 0.5 V; V
DD
= 2.3 V 12 28
V
OL
= 0.5 V; V
DD
= 3.0 V 17 35
V
OL
= 0.5 V; V
DD
= 4.5 V 25 42
I
OL(tot)
Total Low−Level Output Current
(Note 8)
V
OL
= 0.5 V; V
DD
= 4.5 V 400 mA
V
OH
High−Level Output Voltage
(PCA9535E Only)
I
OH
= −3 mA; V
DD
= 1.65 V 1.2
V
I
OH
= −4 mA; V
DD
= 1.65 V 1.1
I
OH
= −8 mA; V
DD
= 2.3 V 1.8
I
OH
= −10 mA; V
DD
= 2.3 V 1.7
I
OH
= −8 mA; V
DD
= 3.0 V 2.6
I
OH
= −10 mA; V
DD
= 3.0 V 2.5
I
OH
= −8 mA; V
DD
= 4.5 V 4.1
I
OH
= −10 mA; V
DD
= 4.5 V 4.0
I
L
Input Leakage Current V
DD
= 5.5 V; V
I
= V
DD
or 0 V $1
mA
C
I/O
Input / Output Capacitance
(Note 9)
3.7 5 pF
INTERRUPT (INT)
I
OL
Low−Level Output Current V
OL
= 0.4 V 6 mA
C
O
Output Capacitance 2.1 5 pF
INPUTS AD0, AD1, AD2
V
IH
High−Level Input Voltage 0.7 x V
DD
V
V
IL
Low−Level Input Voltage 0.3 x V
DD
V
I
L
Leakage Current V
I
= V
DD
or 0 V $1
mA
C
I
Input Capacitance 2.4 5 pF
6. The device is in standby mode after an I2C stop command.
7. The power−on reset circuit resets the I
2
C bus logic with V
DD
< V
POR
and set all I/Os to logic 1 upon power−up. Thereafter, V
DD
must
be lower than 0.2 V to reset the part.
8. Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.
9. The value is not tested, but verified on sampling basis.
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Table 5. AC ELECTRICAL CHARACTERISTICS V
DD
= 1.65 V to 5.5 V; T
A
= −55°C to +125°C, unless otherwise specified.
Symbol
Parameter
Standard Mode Fast Mode Fast Mode +
Unit
Min Max Min Max Min Max
f
SCL
SCL Clock Frequency 0 0.1 0 0.4 0 1.0 MHz
t
BUF
Bus−Free Time between a STOP and START
Condition
4.7 1.3 0.5
ms
t
HD:STA
Hold Time (Repeated) START Condition 4.0 0.6 0.26
ms
t
SU:STA
Setup Time for a Repeated START Condition 4.7 0.6 0.26
ms
t
SU:STO
Setup Time for STOP Condition 4.0 0.6 0.26
ms
t
HD:DAT
Data Hold Time 0 0 0 ns
t
VD:ACK
Data Valid Acknowledge Time (Note 10) 0.3 3.45 0.1 0.9 0.05 0.45
ms
t
VD:DAT
Data Valid Time (Note 11) 300 50 50 450 ns
t
SU:DAT
Data Setup Time 250 100 50 ns
t
LOW
LOW Period of SCL 4.7 1.3 0.5
ms
t
HIGH
HIGH Period of SCL 4.0 0.6 0.26
ms
t
f
Fall Time of SDA and SCL (Notes 13 and 14) 300 20 +
0.1C
b
(Note 12)
300 120 ns
t
r
Rise Time of SDA and SCL 1000 20 +
0.1C
b
(Note 12)
300 120 ns
t
SP
Pulse Width of Spikes Suppressed by Input
Filter (Note 15)
50 50 50 ns
PORT TIMING: C
L
v 100 pF (See Figures 6, 9 and 10)
t
V(Q)
Data Output Valid Time (V
DD
= 4.5 V to 5.5 V)
(V
DD
= 2.3 V to 4.5 V)
(V
DD
= 1.65 V to 2.3 V)
200
350
550
200
350
550
200
350
550
ns
t
SU(D)
Data Input Setup Time 100 100 100 ns
t
H(D)
Data Input Hold Time 1 1 1
ms
INTERRUPT TIMING: C
L
v 100 pF (See Figures 9 and 10)
t
V(INT_N)
Data Valid Time 4 4 4
ms
t
RST(INT_N)
Reset Delay Time 4 4 4
ms
10.t
VD:ACK
= time for Acknowledgment signal from SCL LOW to SDA (out) LOW.
11. t
VD:DAT
= minimum time for SDA data out to be valid following SCL LOW.
12.C
b
= total capacitance of one bus line in pF.
13.A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to V
IL
of the SCL signal) in order to bridge
the undefined region SCL’s falling edge.
14.The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
f
.
15.Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

PCA9535ECMTTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Interface - I/O Expanders 16-BIT I/O EXPANDER
Lifecycle:
New from this manufacturer.
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