I
DD
Specifications
Table 10: DDR2 I
DD
Specifications and Conditions – 256MB
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8)
component data sheet
Parameter Symbol -667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC
(I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
I
DD0
720 640 600 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL =
4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Ad-
dress bus inputs are switching; Data pattern is same as I
DD4W
I
DD1
800 720 680 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
I
DD2P
40 40 40 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
I
DD2Q
320 280 200 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
I
DD2N
320 280 240 mA
Active power-down current: All device banks open;
t
CK =
t
CK (I
DD
); CKE is LOW; Other control and address bus inputs
are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3PF
240 200 160 mA
Slow PDN exit
MR[12] = 1
I
DD3PS
48 48 48
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid com-
mands; Other control and address bus inputs are switching; Data bus inputs
are switching
I
DD3N
400 320 240 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD4W
1520 1280 1000 mA
Operating burst read current: All device banks open; Continuous burst
read, I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
DD4R
1440 1200 920 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC
(I
DD
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
I
DD5
1440 1360 1320 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
I
DD6
40 40 40 mA
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
I
DD
Specifications
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
12
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© 2003 Micron Technology, Inc. All rights reserved.
