Table 12: DDR2 I
DD
Specifications and Conditions – 1GB
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter Symbol -667 -53E -40E Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC
(I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
I
DD0
720 640 560 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL
= CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus in-
puts are switching; Data pattern is same as I
DD4W
I
DD1
800 760 640 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
LOW; Other control and address bus inputs are stable; Data bus inputs are float-
ing
I
DD2P
56 56 56 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus
inputs are floating
I
DD2Q
440 328 280 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus
inputs are switching
I
DD2N
480 360 320 mA
Active power-down current: All device banks open;
t
CK =
t
CK (I
DD
); CKE is LOW; Other control and address bus inputs are
stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3PF
320 240 200 mA
Slow PDN exit
MR[12] = 1
I
DD3PS
80 80 80
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS
MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are switching; Data bus inputs are switching
I
DD3N
560 440 360 mA
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
are switching; Data bus inputs are switching
I
DD4W
1280 1040 880 mA
Operating burst read current: All device banks open; Continuous burst read,
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
I
DD4R
1280 1160 880 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
I
DD5
2080 2000 1760 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
I
DD6
56 56 56 mA
Operating bank interleave read current: All device banks interleaving
reads; I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK
(I
DD
),
t
RC =
t
RC (I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are stable during deselects;
Data bus inputs are switching
I
DD7
2400 2320 2080 mA
256MB, 512MB, 1GB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
I
DD
Specifications
PDF: 09005aef80e2ff8d
htf8c32_64_128x64aypdf - Rev. G 3/10 EN
16
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© 2003 Micron Technology, Inc. All rights reserved.
