ICS1524A
10
ICS1524A Rev F 05/13/10
Name: Output Enable Register
Register: 6 h
Index: Read / Write
Bit Name Bit # Reset Value Description
OE_Pck 0 0 Output Enable for DPACLK Outputs (PECL, Pins 21, 20 )
OE_Tck 1 0 Output Enable for DPACLK Output (SSTL_3 Pin 17)
OE_P2 2 0 Output Enable for CLK Outputs (PECL, Pins 23, 22)
OE_T2 3 0 Output Enable for CLK Output (SSTL_3, Pin 16)
OE_F 4 0 Output Enable for FUNC Output (SSTL_3, Pin 15)
CK2_Inv 5 0 Select CLK Output Source (Pins 23, 22, 16)
Out_Scl 6-7 0 DPACLK Output Scaler (SSTL_3, Pin 17)
Bit Name Description
0 OE_Pck Output Enable for DPACLK Outputs (PECL)
0 = High Z
1 = Enabled
1 OE_Tck Output Enable for DPACLK Output (SSTL_3)
0 = High Z
1 = Enabled
2 OE_P2 Output Enable for CLK Outputs (PECL)
0 = High Z
1 = Enabled
3 OE_T2 Output Enable for CLK Output (SSTL_3)
0 = High Z
1 = Enabled
4 OE_F Output Enable for FUNC Output (SSTL_3)
0 = High Z
1 = Enabled
5 Ck2_Inv Select CLK Output Source (Pins 23, 22, 16)
0 = Half Speed DPA Delayed clock to CLK outputs
1 = Full Speed non-DPA Delayed clock to CLK outputs
6-7 Out_Scl Clock (DPACLK, pin 17) Scaler
00 1
01 2
10 4
11
8
DPACLK Divider
Bit 7
Bit 6
