5
ICS1524A
ICS1524A Rev F 05/13/10
I
2
C Register Map Summary
Register
Index
Name Access Bit Name Bit #
Reset
Value
Description
0h Input Control R / W PDen 0 1 Charge Pump Enable (0=Disable 1=Enable)
PD_Pol 1 0 Charge Pump Enable Polarity
Ref_Pol 2 0 External Reference Polarity (0=Positive Edge, 1=Negative Edge)
Fbk_Pol 3 0 External Feedback Polarity (0=Positive Edge, 1=Negative Edge)
Fbk_Sel 4 0 External Feedback Select (0=Internal Feedback, 1=External)
Func_Sel 5 0 Function Out Select (0=Recovered HSYNC, 1=Input HSYNC)
EnPLS 6 1 Enable PLL Lock/Ref Status Output (0=Disable 1=Enable)
EnDLS 7 0 Enable DPA Lock/Ref Status Output (0=Disable 1=Enable)
1h Loop Control R / W * PFD0-2 0-2 0 Charge Pump Gain
Reserved 3 0 Reserved
PSD0-1 4-5 0 Post-Scaler Divider (0 = /2, 1 = /4, 2 = /8, 3 = /16)
Reserved 6-7 0 Reserved
2h FdBk Div 0 R / W * FBD0-7 0-7 FF PLL FeedBack Divider LSBs (bits 0-7) *
3h FdBk Div 1 R / W * FBD8-11 0-3 F PLL Feedback Divider MSBs (bits 8-11) *
Reserved 4-7 0 Reserved
4h DPA Offset R / W DPA_OS0-5 0-5 0 Dynamic Phase Aligner Offset
Reserved 6 0 Reserved
Fil_Sel 7 1 Loop Filter Select (0=External, 1=Internal)
5h DPA Control R / W ** DPA_Res0-1 0-1 3 DPA Resolution (0=16 delay elements, 1=32, 2=Reserved, 3=64)
Metal_Rev 2-7 0 Metal Mask Revision Number
6h Output Enables R / W OE_Pck 0 1 Output Enable for PECL DPACLK ( 0=High Z, 1=Enabled)
OE_Tck 1 1 Output Enable for STTL_3 DPACLK ( 0=High Z, 1=Enabled)
OE_P2 2 1 Output Enable for PECL CLK ( 0=High Z, 1=Enabled)
OE_T2 3 1 Output Enable for STTL_3 CLK ( 0=High Z, 1=Enabled)
OE_F 4 1 Output Enable for STTL_3 FUNC ( 0=High Z, 1=Enabled)
Ck2_Inv 5 0 Select non-delayed CLK (1) or DPA delayed CLK/2 (0) on CLKx pins
Out_Scl 6-7 0 SSTL DPACLK (Pin 17) Scaler (0 = ÷1, 1 = ÷2, 2 = ÷4, 3 = ÷8)
7h Osc_Div R / W Osc_Div 0-6 0-6 0 Osc Divider modulus
In-Sel 7 1 RESERVED
8h Reset Write DPA 0-3 x Writing xA hex resets DPA and loads working register 5
PLL 4-7 x Writing 5x hex resets PLL and loads working registers 1-3
10h Chip Ver Read Chip Ver 0-7 18 Chip Version 17 hex
11h Chip Rev Read Chip Rev 0-7 01 Chip Revision C2 hex
12h Rd_Reg Read DPA_Lock 0 N/A DPA Lock Status (0=Unlocked, 1=Locked)
PLL_Lock 1 N/A PLL Lock Status (0=Unlocked, 1=Locked)
Reserved 2-7 0 Reserved
* Identifies double-buffered registers. Working registers are loaded during software PLL reset.
** Identifies double-buffered register. Working registers are loaded during software DPA reset.
