ICS1524A
8
ICS1524A Rev F 05/13/10
Name: Feedback Divider 0 Register / Feedback Divider 1 Register
Register: 2h, 3h
Index: Read /Write*
Bit Name Index Bit # Reset Value Description
FBD0-7 2 0-7
FF PLL Feedback Divider LSBs (0-7).* When Bit 0 = 0, then the total
number of clocks per line is even. When Bit 0 = 1, then the total
number of clocks is odd.
FBD8-11 3 0-3 F
PLL Feedback Divider MSBs (8-11)*
Reserved 3 4-7 Reserved
Feedback Divider Modulus
=
*
Double-buffered registers. Actual working registers are loaded during software PLL reset.
See Register 8h for details.
Name: DPA Offset Register
Register: 4h
Index: Read /Write
Bit Name Bit # Reset Value Description
DPA_OS0-5 0-5 0 Dynamic Phase Adjust Offset
Reserved 6 0 Reserved
Fil_Sel 7 0 Loop Filter Select
Bit Name Description
0-5 DPA_OS0-5 Dynamic Phase Adjust Offset.
Selects clock edge offset in discrete steps from zero to one clock period minus one step.
Resolution (number of delay elements per clock cycle) is selected by DPA_Res0-1 (Reg 5:0-1).
Note: Offsets equal to or greater than one clock period are neither recommended nor supported.
Example: For DPA_Res0-1=01H, the clock can be delayed from 0 to 31 steps.
7 Fil_Sel Selects external loop filter (0) or internal loop filter (1).
The use of an external loop filter is strongly recommended for all designs. Typical loop filter
values are 6.8K Ohms for the series resistor, 3300 pF RF-type capacitor for the series capacitor,
and 33 pF for the shunt capacitor.
12 ≤ Feedback Divider Modulus ≤ 4103
The value that is programmed into these two registers, plus a value of 8, defines the total number of clock periods that the ICS
1524 generates between HSYNCs. Program these registers with the total number of horizontal clocks per line minus 8.
3geR2geR
321076543210
+8
