21
ICS1524A
ICS1524A Rev F 05/13/10
Output Timing Diagram
lobmySnoitpircseDgnimiTniMpyTxaMstinU
t
0
yaledFERotCNYSH3.115.1121sn
t
1
yaledkcolcLCEPotFER0.1-8.02.2sn
t
2
t,
3
elcycytudkcolcLCEP540555%
t
4
yaledkcolc3_LTSSotkcolcLCEP2.057.02.1sn
t
5
yaledTUO_CNUFotkcolcLCEP5.19.13.2sn
t
6
kcolc2/LCEPotkcolcLCEP0.13.15.1sn
t
7
yaled2/KLC–3_LTSSotkcolcLCEP1.14.18.1sn
t
8
t,
9
elcycytudkcolcLTSS540555%
*Note: Measured at 3.6V 0°C, 135-MHz output frequency, PECL clock lines to 75 Οηµ termination, SSTL_3 clock lines
unterminated, 20-pF load. Transition times vary based on termination.
Typical Transition Times*
Output Timing*
REF
HSYNC
PECL CLK-
PECL CLK+
SSTL-CLK
FUNC_OUT
t
0
t
R
t
S
t
F
t
5
t
4
t
8
t
9
t
1
t
2
t
3
t
p
PECL DPACLK-
PECL DPACLK+
SSTL-DPACLK
FUNC
t
DPA
t
8
t
9
t
S
t
F
t
4
t
1
t
2
t
3
t
p
lobmySnoitpircseDgnimiTesiRllaFstinU
t
R
FER8.28.1sn
t
P
KLCLCEP0.12.1sn
t
S
KLC-LTSS6.17.0sn
t
F
TUO_CNUF2.10.1sn