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72V36100L10PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
65,536 x 36 and 131,072 x 36
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. X = 15 for the IDT72V36100 and X = 16 for the IDT72V36110.
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
WCLK
SEN
SI
6117 drw20
t
ENH
t
ENS
t
LDS
LD
t
DS
BIT 0
EMPTY OFFSET
BIT X
BIT 0
FULL OFFSET
(1)
t
ENH
BIT X
(1)
t
LDH
t
DH
t
LDH
tRTS
tENH
6117 drw19
tENS
Wx
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
0
- Q
n
tSKEW2
12
1
tPAFS
tHF
tPAES
Wx+1
2
W3
WEN
tENS
W2
(4)
4
5
tENH
W4
tA
tA
tA
W5
tA
(4)
(4)
3
tA
W1
35
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
65,536 x 36 and 131,072 x 36
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode: D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
PAFS
). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW2
, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
WCLK
WEN
PAF
RCLK
(3)
t
PAFS
REN
6117 drw 23
D - (m+1) words in FIFO
(2)
D - m words in FIFO
(2)
1
2
12
D-(m+1) words
in FIFO
(2)
t
PAFS
t
ENH
t
ENS
t
SKEW2
t
ENH
t
ENS
t
CLKL
t
CLKL
RCLK
LD
REN
Q
0
- Q
n
tLDH
tLDS
tENS
DATA IN OUTPUT REGISTER PAE OFFSET
PAF OFFSET
tENH
tENH
tLDH
6117 drw 22
t
CLK
tA
tA
tCLKH tCLKL
WCLK
LD
WEN
D
0 - Dn
6117 drw 21
t
LDS
t
ENS
PAE
OFFSET
PAF
OFFSET
t
DS
t
DH
t
LDH
t
ENH
t
CLK
t
LDH
t
ENH
t
DH
t
CLKH
t
CLKL
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
65,536 x 36 and 131,072 x 36
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4.
tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than t
SKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode:
D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT Mode: D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
CLKH
t
CLKL
t
ENS
t
ENH
WEN
PAF
t
ENS
t
PAFA
D - (m + 1) words
in FIFO
RCLK
t
PAFA
REN
6117 drw25
D - m words
in FIFO
D - (m + 1) words in FIFO
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
t
ENS
n words in FIFO
(2)
,
n+1 words in FIFO
(3)
t
PAES
t
SKEW2
t
PAES
12 12
(4)
REN
6117 drw 24
t
ENS
t
ENH
n+1 words in FIFO
(2)
,
n+2 words in FIFO
(3)
n words in FIFO
(2)
,
n+1 words in FIFO
(3)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

72V36100L10PF8

Mfr. #:
Buy 72V36100L10PF8
Manufacturer:
IDT
Description:
FIFO 64Kx36 3.3V SUPER SYNC II FIFO
Lifecycle:
New from this manufacturer.
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