37
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
TM
36-BIT FIFO
65,536 x 36 and 131,072 x 36
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
2. In FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
ENS
t
ENH
WEN
HF
t
ENS
t
HF
RCLK
t
HF
REN
6117 drw27
t
CLKL
t
CLKH
D/2 words in FIFO
(1)
,
[
+ 1
]
words in FIFO
(2)
D-1
2
D/2 + 1 words in FIFO
(1)
,
[
+ 2
]
words in FIFO
(2)
D/2 words in FIFO
(1)
,
[
+ 1
]
words in FIFO
(2)
D-1
2
D-1
2
WCLK
t
CLKH
t
CLKL
t
ENS
t
ENH
WEN
PAE
t
ENS
t
PAEA
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
RCLK
t
PAEA
REN
6117 drw26
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
