70T3509MS133BPGI Datasheet 70T3509MS133BPG, 70T3509MS133BPGI, 70T3509MS133BPI | P1-P3

JULY 2014

DSC 5682/9

1

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Functional Block Diagram

HIGH-SPEED 2.5V

1024K x 36

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70T3509M

REPEAT

R

A

0R

CNTEN

R

ADS

R

Dout0-8_R

Dout9-17_R

I/O

0R

- I/O

35R

Din_R

ADDR_R

OE

R

BE

3R

BE

2R

BE

1R

BE

0R

R/W

R

CE

0R

CE

1R

1

0

1/0

FT/PIPE

R

1a 0a1b 0b1c 0c1d 0d

dcba

CLK

R

,

Counter/

Address

Reg.

dcba

0/1

0d 1d0c 1c

0b 1b0a 1a

B

W

2

R

B

W

1

R

B

W

0

R

FT/PIPE

R

Counter/

Address

Reg.

CNTEN

L

ADS

L

REPEAT

L

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout18-26_R

Dout27-35_R

B

W

0

L

B

W

1

L

B

W

2

L

B

W

3

L

I/O

0L

-I/O

35L

A

19L

A

0L

Din_L

ADDR_L

OE

L

5682 drw 01

BE

3L

BE

2L

BE

1L

BE

0L

R/W

L

CE

0L

CE

1L

1024K x 36

MEMORY

ARRAY

CLK

L

abcd

FT/PIPE

L

0/1

1d 0d 1c 0c

1b 0b 1a 0a

B

W

3

R

,

JTAG

TCK

TRST

TMS

TDO

TDI

1

0

1/0

0d 1d0c 1c0b 1b0a 1a

abcd

FT/PIPE

L

1/0

INTERRUPT

LOGIC

R/

W

L

CE

0

L

CE1

L

R/

W

R

CE

0

R

CE1

R

INT

L

IN T

R

ZZ

CONTROL

LOGIC

ZZ

L

(1)

ZZ

R

(1)

A

19R

(2)

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆

High-speed data access

– Commercial: 4.2ns (133MHz)(max.)

– Industrial: 4.2ns (133MHz)(max.)

◆

Selectable Pipelined or Flow-Through output mode

◆

Counter enable and repeat features

◆

Interrupt Flags

◆

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHz operation (9.5Gbps bandwidth)

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 133MHz

– Fast 4.2ns clock to data out

NOTE:

1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

2. See Truth Table I for Functionality.

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆

Separate byte controls for multiplexed bus and bus

matching compatibility

◆

Dual Cycle Deselect (DCD) for Pipelined Output Mode

◆

2.5V (±100mV) power supply for core

◆

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

◆

Includes JTAG functionality

◆

Available in a 256-pin Ball Grid Array (BGA)

◆

Common BGA footprint provides design flexibility over

seven density generations (512K to 36M-bit)

◆

Green parts available, see ordering information

6.42

IDT70T3509M

High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Commercial Temperature Range

2

Description:

The IDT70T3509M is a high-speed 1024K x 36 bit synchronous

Dual-Port RAM. The memory array utilizes Dual-Port memory cells to

allow simultaneous access of any address from both ports. Registers on

control, data, and address inputs provide minimal setup and hold times.

The timing latitude provided by this approach allows systems to be

designed with very short cycle times. With an input data register, the

IDT70T3509M has been optimized for applications having unidirectional

or bidirectional data flow in bursts. An automatic power down feature,

controlled by CE0 and CE1, permits the on-chip circuitry of each port to

enter a very low standby power mode.

The 70T3509M can support an operating voltage of either 3.3V or

2.5V on one or both ports, controllable by the OPT pins. The power supply

for the core of the device (VDD) is at 2.5V.

6.42

IDT70T3509M

High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Commercial Temperature Range

3

Pin Configuration

(1,2,3,4)

NOTES:

1. All V

DD pins must be connected to 2.5V power supply.

2. All V

DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is

set to V

SS (0V).

3. All V

SS pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.76mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

7. BP-256 package thickness is 1.76mm nominal. This is thicker than the BC-256 package (1.40mm nominal) used for the lower density IDT dual-port products.

70T3509M BP

BP-256

(5,7)

256-Pin BGA

Top View

(6)

E16

I/O

14R

D16

I/O

16R

C16

I/O

16L

B16

NC

A16

NC

A15

NC

B15

I/O

17L

C15

I/O

17R

D15

I/O

15L

E15

I/O

14L

E14

I/O

13L

D14

I/O

15R

D13

V

DD

C12

A

6L

C14

OPT

L

B14

V

DD

A14

A

0L

A12

A

5L

B12

A

4L

C11

ADS

L

D12

V

DDQR

D11

V

DDQR

C10

CLK

L

B11

REPEAT

L

A11

CNTEN

L

D8

V

DDQR

C8

BE

1L

A9

CE

1L

D9

V

DDQL

C9

BE

0L

B9

CE

0L

D10

V

DDQL

C7

A

7L

B8

BE

3L

A8

BE

2L

B13

A

1L

A13

A

2L

A10

OE

L

D7

V

DDQR

B7

A

9L

A7

A

8L

B6

A

12L

C6

A

10L

D6

V

DDQL

A5

A

14L

B5

A

15L

C5

A

13L

D5

V

DDQL

A4

B4

A

18L

C4

D4

PIPE/

FT

L

A3

A

19L

B3

TDO

C3

V

SS

D3

I/O

20L

D2

I/O

19R

C2

I/O

19L

B2

NC

A2

TDI

A1

NC

B1

I/O

18L

C1

I/O

18R

D1

I/O

20R

E1

I/O

21R

E2

I/O

21L

E3

I/O

22L

E4

V

DDQL

F1

I/O

23L

F2

I/O

22R

F3

I/O

23R

F4

V

DDQL

G1

I/O

24R

G2

I/O

24L

G3

I/O

25L

G4

V

DDQR

H1

I/O

26L

H2

I/O

25R

H3

I/O

26R

H4

V

DDQR

J1

I/O

27L

J2

I/O

28R

J3

I/O

27R

J4

V

DDQL

K1

I/O

29R

K2

I/O

29L

K3

I/O

28L

K4

V

DDQL

L1

I/O

30L

L2

I/O

31R

L3

I/O

30R

L4

V

DDQR

M1

I/O

32R

M2

I/O

32L

M3

I/O

31L

M4

V

DDQR

N1

I/O

33L

N2

I/O

34R

N3

I/O

33R

N4

P1

I/O

35R

P2

I/O

34L

P3

TMS

P4

R1

I/O

35L

R2

NC

R3

TRST

R4

A

18R

T1

NC

T2

TCK

T3

A

19R

T4

P5

A

13R

R5

A

15R

P12

A

6R

P8

BE

1R

P9

BE

0R

R8

BE

3R

T8

BE

2R

P10

CLK

R

T11

CNTEN

R

P11

ADS

R

R12

A

4R

T12

A

5R

P13

A

3R

P7

A

7R

R13

A

1R

T13

A

2R

R6

A

12R

T5

A

14R

T14

A

0R

R14

OPT

R

P14

I/O

0L

P15

I/O

0R

R15

NC

T15

NC

T16

NC

R16

NC

P16

I/O

1L

N16

I/O

2R

N15

I/O

1R

N14

I/O

2L

M16

I/O

4L

M15

I/O

3L

M14

I/O

3R

L16

I/O

5R

L15

I/O

4R

L14

I/O

5L

K16

I/O

7L

K15

I/O

6L

K14

I/O

6R

J16

I/O

8L

J15

I/O

7R

J14

I/O

8R

H16

I/O

10R

H15

IO

9L

H14

I/O

9R

G16

I/O

11R

G15

I/O

11L

G14

I/O

10L

F16

I/O

12L

F14

I/O

12R

F15

I/O

13R

R9

CE

0R

R11

RE PEA T

R

T6

A

11R

T9

CE

1R

A6

A

11L

B10

R/W

L

C13

A

3L

P6

A

10R

R10

R/W

R

R7

A

9R

T10

OE

R

T7

A

8R

,

E5

V

DD

E6

V

DD

E7

INT

L

E8

V

SS

E9

V

SS

E10

V

SS

E11

V

DD

E12

V

DD

E13

V

DDQR

F5

V

DD

F6

NC

F8

V

SS

F9

V

SS

F10

V

SS

F12

V

DD

F13

V

DDQR

G5

V

SS

G6

V

SS

G7

V

SS

G8

V

SS

G9

V

SS

G10

V

SS

G11

V

SS

G12

V

SS

G13

V

DDQL

H5

V

SS

H6

V

SS

H7

V

SS

H8

V

SS

H9

V

SS

H10

V

SS

H11

V

SS

H12

V

SS

H13

V

DDQL

J5

ZZ

R

J6

V

SS

J7

V

SS

J8

V

SS

J9

V

SS

J10

V

SS

J11

V

SS

J12

ZZ

L

J13

V

DDQR

K5

V

SS

K6

V

SS

K7

V

SS

K8

V

SS

L5

V

DD

L6

NC

L7

NC

L8

V

SS

M5

V

DD

M6

V

DD

M7

INT

R

M8

V

SS

N5

V

DDQR

N6

V

DDQR

N7

V

DDQL

N8

V

DDQL

K9

V

SS

K10

V

SS

K11

V

SS

K12

V

SS

L9

V

SS

L10

V

SS

L11

V

SS

L12

V

DD

M9

V

SS

M10

V

SS

M11

V

DD

M12

V

DD

N9

V

DDQR

N10

V

DDQR

N11

V

DDQL

N12

V

DDQL

K13

V

DDQR

L13

V

DDQL

M13

V

DDQL

N13

V

DD

F7

NC

F11

V

SS

5682 drw 02d

,

08/03/04

A

17R

A

17L

A

16L

A

16R

PIPE/

FT

R

70T3509MS133BPGI

70T3509MS133BPGI

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