6.42
IDT70T3509M
High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Commercial Temperature Range
7
Absolute Maximum Ratings
(1)
Symbol Rating Com'l
& Ind
Unit
V
TERM
(VDD)
V
DD Terminal Voltage
with Respect to GND
-0.5 to 3.6 V
V
TERM
(2)
(VDDQ)
V
DDQ Terminal Voltage
with Respect to GND
-0.3 to VDDQ + 0.3 V
V
TE RM
(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to V
DDQ + 0.3 V
T
BIAS
(3)
Temperature Under Bias -55 to +125
o
C
TSTG Storage Temperature -65 to +150
o
C
TJN Junction Temperature +150
o
C
IOUT(For V
DDQ
=
3.3V) DC Output Current 50 mA
I
OUT(For V
DDQ
=
2.5V) DC Output Current 40 mA
5682 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed V
DDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. C
OUT also references CI/O.
Capacitance
(1)
(TA = +25°C, F = 1.0MHZ) BGA ONLY
Symbol Parameter Conditions Max. Unit
C
IN
Input Capacitance V
IN
= 0V 35 pF
C
OUT
(2)
Output Capacitance V
OUT
= 0V 35 pF
5682 tbl 07
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(VDD = 2.5V ± 100mV)
Symbol Parameter Test Conditions
70T3509MS
UnitMin. Max.
|I
LI
| Input Leakage Current
(1)
V
DDQ
= Max., V
IN
= 0V to V
DDQ
___
20 µA
|I
LI
| JTAG & ZZ Input Leakage Current
(1,2)
V
DD =
Max.
,
V
IN
= 0V to V
DD
___
60 µA
|I
LO
| Output Leakage Current
(1,3)
CE
0
= V
IH
and CE
1
= V
IL
, V
OUT
= 0V to V
DDQ
___
20 µA
V
OL
(3.3V) Output Low Voltage
(1)
I
OL
= +4mA, V
DDQ
= Min.
___
0.4 V
V
OH
(3.3V) Output High Voltage
(1)
I
OH
= -4mA, V
DDQ
= Min. 2.4
___
V
V
OL
(2.5V) Output Low Voltage
(1)
I
OL
= +2mA, V
DDQ
= Min.
___
0.4 V
V
OH
(2.5V) Output High Voltage
(1)
I
OH
= -2mA, V
DDQ
= Min. 2.0
___
V
5682 tbl 08
NOTES:
1. V
DDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
6.42
IDT70T3509M
High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Commercial Temperature Range
8
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(3)
(VDD = 2.5V ± 100mV)
NOTES:
1. At f = f
MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V
DD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 30mA (Typ).
5. CE
X = VIL means CE0X = VIL and CE1X = VIH (enabled)
CE
X = VIH means CE0X = VIH and CE1X = VIL (disabled)
CE
X < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V (enabled - CMOS levels)
CE
X > VDDQ - 0.2V means CE0X > VDDQ - 0.2V and CE1X < 0.2V (disabled - CMOS levels)
"X" represents "L" for left port or "R" for right port.
6. I
SB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
70T3509MS133
Com'l
& Ind
Symbol Parameter Test Condition Version Typ.
(4)
Max. Unit
I
DD
Dynamic Operating
Current (Both
Ports Active)
CE
L
and CE
R
= V
IL
,
Outputs Disabled,
f = f
MAX
(1)
COM'L S 800 1120
mA
IND S 800 1370
I
SB1
(6)
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
= CE
R
= V
IH
f = f
MAX
(1)
COM'L S 560 760
mA
IND S 560 940
I
SB2
(6)
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(1)
COM'L S 680 880
mA
IND S 680 1090
I
SB3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CE
0L =
CE
0R
> V
DDQ
- 0.2V and
CE
1L =
CE
1R
< 0.2V,
V
IN
> V
DDQ
- 0.2V or V
IN
< 0.2V, f = 0
(2)
COM'L S 20 60
mA
IND S 20 80
I
SB4
(6)
Full Standby Current
(One Port - CMOS
Level Inputs)
CE
"A"
< 0.2V and CE
"B"
> V
DDQ
- 0.2V
(5)
V
IN
> V
DDQ
- 0.2V or V
IN
< 0.2V
Active Port, Outputs Disabled, f = f
MAX
(1)
COM'L S 680 880
mA
IND S 680 1090
Izz Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZ
L =
ZZ
R =
V
IH
f=f
MAX
(1)
COM'L S 20 60
mA
IND S 20 80
5682 tbl 09
6.42
IDT70T3509M
High-Speed 2.5V 1024K x 36 Dual-Port Synchronous Static RAM Commercial Temperature Range
9
AC Test Conditions (VDDQ - 3.3V/2.5V)
Figure 1. AC Output Test load.
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3
.
0V/GND to 2.4V
GND to 3.0V/GND to 2.4V
2ns
1.5V/1.25V
1.5V/1.25V
Figure 1
5682 tbl 10
1.5V/1.25
50Ω
50Ω
5682 drw 03
10pF
(Tester)
DATA
OUT
,
Δ
Capacitance (pF) from AC Test Load
5682 drw 04
Δ
tCD
(Typical, ns)

70T3509MS133BPGI

Mfr. #:
Manufacturer:
IDT
Description:
SRAM 1024Kx36 STD-PWR 2.5V DUAL PORT RAM
Lifecycle:
New from this manufacturer.
Delivery:
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