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M48T58Y-70PC1

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M48T58, M48T58Y WRITE mode
Doc ID 2412 Rev 8 13/33
Table 4. WRITE mode AC characteristics
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
M48T58/Y
Unit
Min Max
t
AVAV
WRITE cycle time 70 ns
t
AVWL
Address valid to WRITE enable low 0 ns
t
AVE1L
Address valid to chip enable 1 low 0 ns
t
AVE2H
Address valid to chip enable 2 high 0 ns
t
WLWH
WRITE enable pulse width 50 ns
t
E1LE1H
Chip enable 1 low to chip enable 1 high 55 ns
t
E2HE2L
Chip enable 2 high to chip enable 2 low 55 ns
t
WHAX
WRITE enable high to address transition 0 ns
t
E1HAX
Chip enable 1 high to address transition 0 ns
t
E2LAX
Chip enable 2 low to address transition 0 ns
t
DVWH
Input valid to WRITE enable high 30 ns
t
DVE1H
Input valid to chip enable 1 high 30 ns
t
DVE2L
Input valid to chip enable 2 low 30 ns
t
WHDX
WRITE enable high to input transition 5 ns
t
E1HDX
Chip enable 1 high to input transition 5 ns
t
E2LDX
Chip enable 2 low to input transition 5 ns
t
WLQZ
(2)(3)
2. C
L
= 5 pF.
3. If E1
goes low or E2 high simultaneously with W going low, the outputs remain in the high impedance
state.
Write enable low to output Hi-Z 25 ns
t
AVWH
Address valid to WRITE enable high 60 ns
t
AVE1H
Address valid to chip enable 1 high 60 ns
t
AVE2L
Address valid to chip enable 2 low 60 ns
t
WHQX
(2)(3)
WRITE enable high to output transition 5 ns
Data retention mode M48T58, M48T58Y
14/33 Doc ID 2412 Rev 8
5 Data retention mode
With valid V
CC
applied, the M48T58/Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs
become high impedance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the
user can be assured the memory will be in a write protected state, provided the V
CC
fall time
is not less than t
F
. The M48T58/Y may respond to transient noise spikes on V
CC
that reach
into the deselect window during the time the device is sampling V
CC
. Therefore, decoupling
of the power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T58/Y for an accumulated period of at least 7 years when V
CC
is less than V
SO
. As
system power returns and V
CC
rises above V
SO
, the battery is disconnected, and the power
supply is switched to external V
CC
. Write protection continues until V
CC
reaches V
PFD
(min)
plus t
rec
(min). E1 should be kept high or E2 low as V
CC
rises past V
PFD
(min) to prevent
inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume
t
rec
after V
CC
exceeds V
PFD
(max).
For more information on battery storage life refer to the application note AN1012.
M48T58, M48T58Y Clock operations
Doc ID 2412 Rev 8 15/33
6 Clock operations
6.1 Reading the clock
Updates to the TIMEKEEPER
®
registers (see Ta bl e 5) should be halted before clock data is
read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM
array are only data registers and not the actual clock counters, so updating the registers can
be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register 1FF8h. As
long as a '1' remains in that position, updating is halted.
After a halt is issued, the registers reflect the count; that is, the day, date, and the time that
were current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
6.2 Setting the clock
Bit D7 of the control register (1FF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like the
READ bit, halts updates to the TIMEKEEPER
®
registers. The user can then load them with
the correct day, date, and time data in 24-hour BCD format (see Ta bl e 5). Resetting the
WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual
TIMEKEEPER counters and allows normal operation to resume. The bits marked as '0' in
Table 5 on page 16 must be written to '0' to allow for normal TIMEKEEPER and RAM
operation. After the WRITE bit is reset, the next clock update will occur within one second.
See the application note AN923 “TIMEKEEPER Rolling Into the 21st Century” for
information on century rollover.
6.3 Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. The M48T58/Y is shipped from STMicroelectronics with the STOP bit set to a '1.'
When reset to a '0,' the M48T58/Y oscillator starts within 1 second.
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M48T58Y-70PC1

Mfr. #:
Buy M48T58Y-70PC1
Manufacturer:
STMicroelectronics
Description:
Real Time Clock 64K (8Kx8) 70ns
Lifecycle:
New from this manufacturer.
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