LT4250L/LT4250H
11
4250lhfa
APPLICATIONS INFORMATION
Undervoltage and Overvoltage Detection
The UV (Pin 3) and OV (Pin 2) pins can be used to detect
undervoltage and overvoltage conditions at the power sup-
ply input. The UV and OV pins are internally connected to
analog comparators with 130mV and 20mV of hysteresis
respectively. When the UV pin falls below its threshold or
the OV pin rises above its threshold, the GATE pin is im-
mediately pulled low. The GATE pin will be held low until
UV is high and OV is low.
The undervoltage and overvoltage trip voltages can be
programmed using a three resistor divider as shown in
Figure 11. With R4 = 549k, R5 = 6.49k and R6 = 10K, the
undervoltage threshold is set to 38.5V (with a 43V release
from undervoltage) and the overvoltage threshold is set
to 71V. The resistor divider will also gain up the hysteresis
at the UV pin and OV pin to 4.5V and 1.2V at the input
respectively.
PWRGD/PWRGD Output
The PWRGD/PWRGD output can be used to directly enable
a power module when the input voltage to the module is
within tolerance. The LT4250L has a PWRGD output for
modules with an active low enable input, and the LT4250H
has a PWRGD output for modules with an active high
enable input.
When the DRAIN voltage of the LT4250H is high with
respect to V
EE
(Figure 12) or the GATE voltage is low, the
internal transistor Q3 is turned off and I
1
and Q2 clamp
the PWRGD pin one SAT drop (≈0.3V) above the DRAIN
pin.Transistor Q2 sinks the module’s pull-up current and
the module turns off.
When the DRAIN voltage drops below V
DL
and the GATE
voltage is high, Q3 will turn on, shorting the bottom of
I
1
to DRAIN and turning Q2 off. The pull-up current in
the module pulls the PWRGD pin high and enables the
module.
When the DRAIN voltage of the LT4250L is high with
respect to V
EE
or the GATE voltage is low, the internal
pull-down transistor Q2 is off and the PWRGD pin is in a
high impedance state (Figure 13). The PWRGD pin will be
pulled high by the module’s internal pull-up current source,
turning the module off. When the DRAIN voltage drops
below V
DL
and the GATE voltage is high, Q2 will turn on
and the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED
oroptoisolator to indicate that the power is good as shown
in Figure 14.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 18V,
the GATE pin voltage is regulated at 13.5V above V
EE
.
The gate voltage will be no greater than 18V for supply
voltages up to 80V.
V
EE
V
DD
LT4250L/LT4250H
R4
R5
R6
4
4250 F11
OV
–48V RTN
3
2
–48V
UV
8
V
UV
= 1.255
R4 + R5+ R6
R5 + R6
()
V
OV
= 1.255
R4 + R5+ R6
R6
()
–48V RTN
(SHORT PIN)
+
V
EE
V
DD
LT4250H
SENSE
C1
C3
Q1
R2
R3
C2
R4
R5
R6
R1
4
3
2
OV
–48V RTN
–48V
UV
56
8
1
7
GATE
4250 F12
PWRGD
DRAIN
V
EE
Q3
ACTIVE HIGH
ENABLE MODULE
V
OUT
+
V
OUT
–
V
IN
+
V
IN
–
ON/OFF
–48V RTN
(SHORT PIN)
*
* DIODES INC. SMAT70A
43
21
Q2
V
DL
V
GH
+
–
+
–
+
–
+
–
GATE
ΔV
GATE
I
1
Figure 11. Undervoltage and Overvoltage Sensing
Figure 12. Active High Enable Module
