LT4250L/LT4250H
5
4250lhfa
PIN FUNCTIONS
for this pin is 1.5μs. Add an external capacitor to this pin
for additional filtering.
V
EE
(Pin 4): Negative Supply Voltage Input. Connect to
the lower potential of the power supply.
SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense
resistor placed in the supply path between V
EE
and SENSE,
the overcurrent condition will pull down the GATE pin and
regulate the voltage across the resistor to be 50mV. If
the overcurrent condition exists for more than 500μs the
electronic circuit breaker will trip and turnoff the external
MOSFET.
If the current limit value is set to twice the normal operating
current, only 25mV is dropped across the sense resistor
during normal operation. To disable the current limit feature,
V
EE
and SENSE can be shorted together.
GATE (Pin 6): Gate Drive Output for the External N-channel
MOSFET. The GATE pin will go high when the following
start-up conditions are met: the UV pin is high, the OV pin
is low, (V
SENSE
– V
EE
) < 50mV and the V
DD
pin is greater
than V
UVLOH
. The GATE pin is pulled high by a 45μA cur-
rent source and pulled low with a 50mA current source.
During current limit the GATE pin is pulled low using a
100mA current source.
DRAIN (Pin 7): Analog Drain Sense Input. Connect this
pin to the drain of the external N-channel MOSFET and
the V
–
pin of the power module. When the DRAIN pin is
below V
DL
, the PWRGD/PWRGD pin will latch to indicate
the switch is on.
V
DD
(Pin 8): Positive Supply Voltage Input. Connect this
pin to the higher potential of the power supply inputs and
the V
+
pin of the power module. An undervoltage lockout
circuit disables the chip until the V
DD
pin is greater than
the 16V V
UVLOH
threshold.
PWRGD/PWRGD (Pin 1): Power Good Output Pin. This pin
will latch a power good indication when V
DRAIN
is within
V
DL
of V
EE
and V
GATE
is within V
GH
of ΔV
GATE
. This pin
can be connected directly to the enable pin of a power
module.
When the DRAIN pin of the LT4250L is above V
EE
by more
than V
DL
or V
GATE
is more than V
GH
from ΔV
GATE
, the
PWRGD pin will be high impedance, allowing the pull-up
current of the module’s enable pin to pull the pin high and
turn the module off. When V
DRAIN
drops below V
DL
and
V
GATE
rises above V
GH
, the PWRGD pin sinks current to
V
EE
, pulling the enable pin low and turning on the module.
This condition is latched until the GATE pin is turned off
via the UV, OV, UVLO or the electronic circuit breaker.
When the DRAIN pin of the LT4250H is above V
EE
by more
than V
DL
or V
GATE
is more than V
GH
from ΔV
GATE
, the
PWRGD pin will sink current to the DRAIN pin which pulls
the module’s enable pin low, forcing it off. When V
DRAIN
drops below V
DL
and V
GATE
rises above V
GH
, the PWRGD
sink current is turned off, allowing the module’s pull-up
current to pull the enable pin high and turn on the module.
This condition is latched until the GATE pin is turned off
via the UV, OV, UVLO or the electronic circuit breaker.
OV (Pin 2): Analog Overvoltage Input. When OV is pulled
above the 1.255V threshold, an overvoltage condition is
detected and the GATE pin will be immediately pulled low.
The GATE pin will remain low until OV drops below the
1.235V threshold.
UV (Pin 3): Analog Undervoltage Input. When UV is pulled
below the 1.125V threshold, an undervoltage condition
is detected and the GATE pin will be immediately pulled
low. The GATE pin will remain low until UV rises above
the 1.255 threshold.
The UV pin is also used to reset the electronic circuit
breaker. If the UV pin is cycled low and high following the
trip of the circuit breaker, the circuit breaker is reset and a
normal power-up sequence will occur. The response time
