LTC3863
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applicaTions inForMaTion
The SENSE pin is a high impedance input with a maximum
leakage of ±2µA. Since the LTC3863 is a peak current
mode controller, noise on the SENSE pin can create pulse
width jitter. Careful attention must be paid to the layout of
R
SENSE
. To ensure the integrity of the current sense signal,
V
SENSE
, the traces from V
IN
and SENSE pins should be
short and run together as a differential pair and Kelvin
(4-wire) connected across R
SENSE
(Figure 3).
The LTC3863 has internal filtering of the current sense
voltage which should be adequate in most applications.
However, adding a provision for an external filter offers
added flexibility and noise immunity, should it be neces
-
sary. The
filter can be created by placing a resistor from the
R
SENSE
resistor to the SENSE pin and a capacitor across
the V
IN
and SENSE pins.
Power MOSFET Selection
The LTC3863 drives a P-channel power MOSFET that
serves as the main switch for the nonsynchronous
inverting converter. Important P-channel power MOSFET
parameters include drain-to-source breakdown voltage
BV
DSS
, threshold voltage V
GS(TH)
, on-resistance R
DS(ON)
,
gate-to-drain reverse transfer capacitance C
RSS
, maximum
drain current I
D(MAX)
, and the MOSFET’s thermal resistance
θ
JC(MOSFET)
and θ
JA(MOSFET)
.
The drain-to-source breakdown voltage must meet the
following condition:
BV
DSS
> V
IN(MAX)
+ |V
OUT
| + V
D
The gate driver bias voltage V
IN
-V
CAP
is set by an internal
LDO regulator. In normal operation, the CAP pin will be
regulated to 8V below V
IN
. A minimum 0.1µF capacitor
is required across the V
IN
and CAP pins to ensure LDO
stability. If required, additional capacitance can be added
to accommodate higher gate currents without voltage
droop. In shutdown and Burst Mode operation, the CAP
LDO is turned off. In the event of CAP leakage to ground,
the CAP voltage is limited to 9V by a weak internal clamp
from V
IN
to CAP. As a result, a minimum 10V V
GS
rated
MOSFET is required.
The power dissipated by the P-channel MOSFET when the
LTC3863 is in continuous conduction mode is given by:
P
PMOS
D
I
OUT
1–D
2
ρ
T
R
DS(ON)
+
f C
MILLER
V
IN
+|V
OUT
|+V
D
( )
2
2
I
OUT
1–D
R
DN
V
IN
V
CAP
V
MILLER
( )
+
R
UP
V
MILLER
where D is duty factor, R
DS(ON)
is on-resistance of
P-channel MOSFET, ρ
T
is temperature coefficient of on-
resistance, R
DN
is the pull-down driver resistance specified
at 0.9Ω typical and R
UP
is the pull-up driver resistance
specified attypical. V
MILLER
is the Miller effective V
GS
voltage and is taken graphically from the power MOSFET
data sheet.
Figure 3. Inductor Current Sensing
V
IN
R
SENSE
LTC3863
V
IN
SENSE
R
F
MP
OPTIONAL
FILTERING
3863 F03
C
F
LTC3863
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Figure 4. (4a) Typical P-Channel MOSFET Gate Charge
Characteristics and (4b) Test Set-Up to Generate Gate
Charge Curve
S
D
G
V
SD(TEST)
R
LOAD
I
GATE
3863 F04
MILLER EFFECT
Q
IN
(4a) (4b)
a b
C
MILLER
= (Q
B
– Q
A
)/V
SD(TEST)
V
SG
+
applicaTions inForMaTion
The power MOSFET input capacitance, C
MILLER
, is the most
important selection criteria for determining the transition
loss term in the P-channel MOSFET but is not directly speci
-
fied on MOSFET data sheets. C
MILLER
is a combination of
several components, but it can be derived from the typical
gate charge curve included on most data sheets (Figure4).
The curve is generated by forcing a constant current out
of the gate of a common-source connected P-channel
MOSFET that is loaded with a resistor, and then plotting
the gate voltage versus time. The initial slope is the effect
of the gate-to-source and gate-to-drain capacitances. The
flat portion of the curve is the result of the Miller multipli
-
cation effect of the drain-to-gate capacitance as the drain
voltage rises across the resistor load. The Miller charge
(the increase in coulombs on the horizontal axis from a to
b while the curve is flat) is specified for a given V
SD
test
voltage, but can be adjusted for different V
SD
voltages by
multiplying by the ratio of the adjusted V
SD
to the curve
specified V
SD
value. A way to estimate the C
MILLER
term
is to take the change in gate charge from points a and b
(or the parameter Q
GD
on a manufacturer’s data sheet)
and dividing it by the specified V
SD
test voltage, V
SD(TEST)
.
C
MILLER
Q
GD
V
SD(TEST)
The term with C
MILLER
accounts for transition loss, which
is highest at high input voltages. For V
IN
< 20V, the high
current efficiency generally improves with larger MOSFETs,
while for V
IN
> 20V, the transition losses rapidly increase
to the point that the use of a higher R
DS(ON)
device with
lower C
MILLER
actually provides higher efficiency.
Schottky Diode Selection
When the P-channel MOSFET is turned off, a power
Schottky diode is required to function as a commutating
diode to carry the inductor current. The average forward
diode current is independent of duty factor and is de
-
scribed as:
I
F(AVG)
= I
OUT
The worst-case condition for diode conduction is a short-
circuit condition where the Schottky must handle the
maximum current as its duty factor approaches 100% (and
the P-channel MOSFET’s duty factor approaches 0%). The
diode therefore must be chosen carefully to meet worst-
case voltage and current requirements. A good practice
is to choose a diode that has a forward current rating two
times higher than I
OUT(MAX)
.
Once the average forward diode current is calculated, the
power dissipation can be determined. Refer to the Schottky
diode data sheet for the power dissipation
, P
DIODE
, as a
function of average forward current, I
F(AVG)
. P
DIODE
can
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also be iteratively determined by the two equations below,
where V
F(IOUT
,
TJ)
is a function of both I
F(AVG)
and junction
temperature T
J
. Note that the thermal resistance, θ
JA(DIODE)
,
given in the data sheet is typical and can be highly layout
dependent. It is therefore important to make sure that the
Schottky diode has adequate heat sinking.
T
J
P
DIODE
θ
JA(DIODE)
P
DIODE
I
F(AVG)
V
D(IOUT,TJ)
The Schottky diode forward voltage is a function of both
I
F(AVG)
and T
J
, so several iterations may be required to
satisfy both equations. The Schottky forward voltage,
V
D
, should be taken from the Schottky diode data sheet
curve showing instantaneous forward voltage. The forward
voltage will change as a function of both T
J
and I
F(AVG)
.
The nominal forward voltage will also tend to increase as
the reverse breakdown voltage increases. It is therefore
advantageous to select a Schottky diode appropriate to the
input voltage requirements. The diode reverse breakdown
voltage must meet the following condition:
V
R
> V
IN(MAX)
+ |V
OUT
|
C
IN
and C
OUT
Selection
The input and output capacitance, C
IN
/C
OUT
, are required
to filter the square wave current through the P-channel
MOSFET and diode respectively. Use a low ESR capacitor
sized to handle the maximum RMS current:
I
CIN(RMS)
=I
COUT(RMS)
=I
OUT
|V
OUT
|+V
D
V
IN
The formula shows that the RMS current is greater than
the maximum I
OUT
when V
OUT
is greater than V
IN
. Choose
capacitors with higher RMS rating with sufficient margin.
Note that ripple current ratings from capacitor manufac
-
turers are often based on only 2000 hours of life, which
makes it advisable to derate the capacitor.
The selection of C
OUT
is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The V
OUT
is approximately bounded by:
V
OUT
I
L(PEAK)
ESR+
I
OUT
D
f C
OUT
where I
L(PEAK)
is the peak inductor current and it’s given as:
I
L(PEAK)
=
I
OUT
V
IN
+|V
OUT
|+V
D
( )
V
IN
+
V
IN
|V
OUT
|+V
D
( )
2L f V
IN
+|V
OUT
|+V
D
( )
Since I
L(PEAK)
and D reach their maximum values at mini-
mum V
IN
, the output voltage ripple is highest at minimum
V
IN
and maximum I
OUT
. Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering
and has the necessar
y RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, specialty polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
packages. Specialty polymer capacitors offer very low
ESR but have lower specific capacitance than other types.
Tantalum capacitors have the highest specific capacitance,
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications provided that
consideration is given to ripple current ratings and long-
term reliability. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient and
audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing. When used as input
capacitors, care must be taken to ensure that ringing from
inrush currents and
switching does not pose an overvolt-
age
hazard to the power switch and controller. To
dampen
input voltage transients, add a smallF to 40μF aluminum
electrolytic capacitor with an ESR in the range of 0.5Ω to
2Ω. High performance through-hole capacitors may also
be used, but an additional ceramic capacitor in parallel
is recommended to reduce the effect of lead inductance.

LTC3863IDE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 60V Low IQ Inverting Buck-Boost DC/DC PMOS Controller
Lifecycle:
New from this manufacturer.
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