LTC3863
7
3863fa
For more information www.linear.com/3863
Typical perForMance characTerisTics
GATE Bias LDO (V
IN
- V
CAP
) Load
Regulation
GATE Bias LDO (V
IN
- V
CAP
)
Dropout Behavior
Current Sense Voltage Over ITH
Voltage
Current Sense Voltage Over
Temperature
SS Pin Pull-Up Current Over
Temperature
RUN Pin Pull-Up Current Over
Temperature
Free Running Frequency Over
Input Voltage
Free Running Frequency Over
Temperature
Frequency Foldback % Over
Feedback Voltage
T
A
= 25°C, unless otherwise noted.
V
IN
(V)
0
300
f (kHz)
450
600
550
500
400
350
10
20 30 40 50
3863 G19
60
FREQ = 0V
FREQ = OPEN
V
FB
(mV)
0
0
FREQUENCY FOLDBACK (%)
60
120
100
80
40
20
200
400 600
3863 G21
800
I
GATE
(mA)
0
–3.5
(V
IN
- V
CAP
) REGULATION (%)
–2.0
0.5
–1.0
–0.5
0.0
–1.5
–2.5
–3.0
5
10 15
3863 G22
20
I
GATE
(mA)
0
–0.5
(V
IN
- V
CAP
) DROPOUT (V)
0.1
V
IN
= 5V
–0.1
0.0
–0.2
–0.3
–0.4
5
10 15
3863 G23
20
TEMPERATURE
(°C)
–75
90
CURRENT LIMIT SENSE VOLTAGE (mV)
100
98
94
92
96
–25
25 75 125
3863 G25
175
TEMPERATURE
(°C)
–75
0.25
RUN PULL-UP CURRENT (µA)
0.65
0.55
0.35
0.45
–25
25 75 125
3863 G27
175
V
RUN
= 0V
TEMPERATURE
(°C)
–75
300
f (kHz)
450
600
550
500
400
350
–25
25 75 125
3864 G20
175
FREQ = 0V
FREQ = OPEN
TEMPERATURE
(°C)
–75
6
SS PULL-UP CURRENT (µA)
14
12
8
10
–25
25 75 125
175
V
SS
= 0V
ITH VOLTAGE
(V)
0
–10
CURRENT SENSE VOLTAGE (mV)
100
80
90
40
30
20
10
0
70
60
50
0.4
0.8 1.2 1.6
3863 G24
2
Burst Mode OPERATION
PULSE-SKIPPING
LTC3863
8
3863fa
For more information www.linear.com/3863
pin FuncTions
PLLIN/MODE (Pin 1): External Reference Clock Input
and Burst Mode Enable/Disable. When an external clock
is applied to this pin, the internal phase-locked loop will
synchronize the turn-on edge of the gate drive signal with
the rising edge of the external clock. When no external
clock is applied, this input determines the operation during
light loading. Floating this pin selects low I
Q
(50µA) Burst
Mode operation. Pulling to ground selects pulse-skipping
mode operation.
FREQ (Pin 2): Switching Frequency Setpoint Input. The
switching frequency is programmed by an external set-
point resistor R
FREQ
connected between the FREQ pin and
signal ground. An internal 20µA current source creates
a voltage across the external setpoint resistor to set the
internal oscillator frequency. Alternatively, this pin can
be driven directly by a DC voltage to set the oscillator
frequency. Grounding selects a fixed operating frequency
of 350kHz. Floating selects a fixed operating frequency
of 535kHz.
SGND (Pin 3): Ground Reference for Small-Signal Analog
Component (Signal Ground). Signal ground should be
used as the common ground for all small-signal analog
inputs and compensation components. Connect the signal
ground to the power ground (ground reference for power
components) only at one point using a single PCB trace.
SS (
Pin 4): Soft-Start and External Tracking Input. The
LTC3863 regulates the feedback voltage to the smaller of
0.8V or the voltage on the SS pin. An internal 10μA pull-up
current source is connected to this pin. A capacitor to
ground
at this pin sets the ramp time to the final regulated
output voltage. Alternatively, another voltage supply con
-
nected through
a resistor divider to this pin allows the
output to track the other supply during start-up.
V
FB
(Pin 5): Output Feedback Sense. A resistor divider
from the regulated output point to this pin sets the output
voltage. The LTC3863 will nominally regulate V
FB
to the
internal reference value of 0.8V. If V
FB
is less than 0.4V,
the switching frequency will linearly decrease and fold
back to about one-fifth of the internal oscillator frequency
to reduce the minimum duty cycle.
ITH (Pin 6): Current Control Threshold and Controller
Compensation Point. This pin is the output of the error
amplifier and the switching regulator’s compensation
point. The voltage ranges from 0V to 2.9V, with 0.8V
corresponding to zero sense voltage (zero current). R
ITH
should never be less than 10K to avoid large signal com-
pensation issues.
For further detail please see the section
Large Signal Effects on ITH.
V
FBN
(Pin 7): Feedback Input for an Inverting PWM Control-
ler. Connect
V
FBN
to the center of a resistor divider between
the output and V
FB
. The resistor divider is comprised of
R
FB1
, placed from the V
OUT
pin to V
FBN
pin and R
FB2
, placed
from the V
FBN
pin to V
FB
. It is recommended to set R
FB2
to be greater than 8K, please see the Output Voltage Pro-
gramming section
for further detail. The V
FBN
threshold is
0V. To defeat the inverting amplifier and use the LTC3863
as an LTC3864 (noninverting buck), tie V
FBN
> 2V.
RUN (Pin 8): Digital Run Control Input. A RUN voltage
above the 1.26V threshold enables normal operation, while
a voltage below the threshold shuts down the controller.
An internal 0.4µA current source pulls the RUN pin up to
about 3.3V. The RUN pin can be connected to an external
power supply up to 60V.
CAP (Pin 9): Gate Driver (–) Supply. A low ESR ceramic
bypass capacitor of at least 0.1µF or 10X the effective
C
MILLER
of the P-channel power MOSFET, is required
from V
IN
to this pin to serve as a bypass capacitor for the
internal regulator. To ensure stable low noise operation, the
bypass capacitor should be placed adjacent to the V
IN
and
CAP pins and connected using the same PCB metal layer.
SENSE (Pin 10): Current Sense Input. A sense resistor,
R
SENSE
, from the V
IN
pin to the SENSE pin sets the maxi-
mum current
limit. The peak inductor current limit is equal
to 95mV/R
SENSE
. For accuracy, it is important that the V
IN
pin and the SENSE pin route directly to the current sense
resistor and make a Kelvin (4-wire) connection.
V
IN
(Pin 11): Chip Power Supply. A minimum bypass
capacitor of 0.1µF is required from the V
IN
pin to power
ground. For best performance use a low ESR ceramic
capacitor placed near the V
IN
pin.
LTC3863
9
3863fa
For more information www.linear.com/3863
+
EA
(G
m
= 1.8mS)
0.8V
EN
10µA
LOGIC
CONTROL
LDO
IN
OUT
PLL
SYSTEM
Q
S R
MODE/CLOCK
DETECT
VCO
OV
0.88V
SLOPE
COMPENSATION
3.25V
GATE
CAP
SS
V
FBN
V
IN
– 8V
SENSE
V
IN
1.26V
+
+
PLLIN/MODE
PGND
C
CAP
MP
D1
0.5µA
UVLO
R
FREQ
SGND
FREQ
RUN
RUN
0.4µA
20µA
3863 FD
+
+
DRV
CLOCK
+
+
O.425V
Burst Mode
OPERATION
+
ITH
R
ITH
C
ITH1
L
C
SS
C
FB2
C
IN
V
IN
R
SENSE
C
OUT
V
OUT
V
FB
R
FB1
R
FB2
ICMP
+
pin FuncTions
FuncTional DiagraM
GATE (Pin 12): Gate Drive Output for External P-Channel
MOSFET. The gate driver bias supply voltage (V
IN
-V
CAP
)
is regulated to 8V when V
IN
is greater than 8V. The gate
driver is disabled when (V
IN
-V
CAP
) is less than 3.5V (typi-
cal), 3.8V maximum
in start-up and 3.25V (typical) 3.5V
maximum in normal operation.
PGND (Exposed Pad Pin 13): Ground Reference for Power
Components (Power Ground). The PGND exposed pad must
be soldered to the circuit board for electrical contact and
for rated thermal performance of the package. Connect
signal ground to power ground only at one point using a
single PCB trace.

LTC3863IDE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 60V Low IQ Inverting Buck-Boost DC/DC PMOS Controller
Lifecycle:
New from this manufacturer.
Delivery:
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