ADF4156 Data Sheet
Rev. E | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ............................................................ 5
Thermal Impedance ..................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description ........................................................................... 8
Reference Input Section ............................................................... 8
RF Input Stage ............................................................................... 8
RF INT Divider ............................................................................. 8
INT, FRAC, MOD, and R Relationship ..................................... 8
RF R-Counter ................................................................................ 8
Phase Frequency Detector (PFD) and Charge Pump .............. 9
MUXOUT and Lock Detect ........................................................ 9
Input Shift Registers ..................................................................... 9
Program Modes ............................................................................ 9
Register Maps .................................................................................. 10
FRAC/INT Register, R0 ............................................................. 11
Phase Register, R1 ...................................................................... 12
MOD/R Register, R2 .................................................................. 13
Function Register, R3 ................................................................. 15
CLK DIV Register, R4 ................................................................ 16
Reserved Bits ............................................................................... 16
Initialization Sequence .............................................................. 16
RF Synthesizer: A Worked Example ........................................ 17
Modulus ....................................................................................... 17
Reference Doubler and Reference Divider ............................. 17
12-Bit Programmable Modulus ................................................ 17
Fast Lock Times with the ADF4156 ........................................ 17
Spur Mechanisms ....................................................................... 19
Spur Consistency and Fractional Spur Optimization ........... 19
Phase Resync ............................................................................... 20
Low Frequency Applications .................................................... 20
Filter Design—ADIsimPLL ....................................................... 20
Interfacing ................................................................................... 21
PCB Design Guidelines for Chip Scale Package .................... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
10/13—Rev. D. to Rev. E
Changes to Table 3 ............................................................................ 5
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
3/12—Rev. C to Rev. D
Changes to Table 1 ............................................................................ 3
Changes to Ordering Guide .......................................................... 22
9/11—Rev. B to Rev. C
Changes to Noise Characteristics Parameter ................................ 3
4/11—Rev. A to Rev. B
Changes to Product Title, Features Section and General
Description Section .......................................................................... 1
Changes to RF Input Frequency RF
IN
Parameter, Table 1 ........... 3
Changes to Figure 4 and Table 5 ..................................................... 6
5/09—Rev. 0 to Rev. A
Added Low Power Sleep Mode Parameter and Changes to
Endnote 4, Table 1 ............................................................................ 3
Change to Figure 9 Caption ............................................................ 7
Change to Program Modes Section ................................................ 9
Changes to Figure 16 ...................................................................... 10
Changes to Figure 17 ...................................................................... 11
Changes to CSR Enable Section ................................................... 13
Changes to Figure 19 ...................................................................... 14
Changes to Function Register, R3 Section and Figure 20 ......... 15
Changes to 12-Bit Clock Divider Value Section, to
Clock Divider Mode Section, and to Figure 21 .......................... 16
Changes to Reference Doubler and Reference Divider Section
and to Fast Lock Times with the ADF4156 Section .................. 17
Added Figure 22 and Figure 23; Renumbered Sequentially ..... 19
Change to Phase Resync Section .................................................. 20
Changes to Interfacing Section and to PCB Design Guidelines
for Chip Scale Package Section ..................................................... 21
Changes to Outline Dimensions .................................................. 23
Changes to Ordering Guide .......................................................... 23
5/06—Revision 0: Initial Version
