Data Sheet ADF4156
Rev. E | Page 21 of 24
INTERFACING
The ADF4156 has a simple SPI-compatible serial interface for
writing to the device. CLOCK, DATA, and LE control the data
transfer. When latch enable (LE) is high, the 29 bits that have
been clocked into the input register on each rising edge of serial
clock are transferred to the appropriate latch. The maximum
allowable serial clock rate is 20 MHz. See Figure 2 for the timing
diagram and Table 6 for the latch truth table.
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the lead frame chip scale package (CP-20-6) are
rectangular. The printed circuit board pad for these lands should be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. The package land should be centered
on the pad to ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that shorting
is avoided.
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad on a 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz of
copper to plug the via. In addition, the printed circuit board
thermal pad should be connected to AGND.
