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ADF4156BCPZ-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
ADF4156 Data Sheet
Rev. E | Page 6 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
1
6
15
14
13
12
1
1
10
9
C
P
CPGND
AGND
A
V
DD
RF
IN
A
R
F
IN
B
R
SE
T
DV
D
D
M
U
XO
U
T
L
E
CE
REF
IN
DGND
CLOCK
DATA
V
P
ADF4156
TOP VIEW
(Not t
o
Sca
le
)
05863-003
Figure 3. TSSOP Pin Configuration
PIN 1
INDIC
A
T
OR
1
CPGND
2
AGND
3AGND
4
RF
IN
B
5
RF
IN
A
13 D
ATA
14
LE
15 MUXOUT
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
12
CLOCK
1
1 CE
6AV
DD
7AV
DD
8REF
IN
10DGND
9DGND
18
V
P
19
R
SET
20
CP
17
DV
DD
16
DV
DD
TOP VIEW
(Not to Scale)
ADF4156
05863-004
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 R
SET
Connecting a resistor between this pin and ground sets the maximum charge-pump output current. The
relationship between I
CP
and R
SET
is
SET
CPmax
R
I
5.25
=
where R
SET
= 5.1 kΩ and I
CPmax
= 5 mA.
2 20 CP
Charge-Pump Output. When enabled, this pin provides ±I
CP
to the external loop filter, which in turn drives
the external VCO.
3 1 CPGND Charge-Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5
4
RF
IN
B
Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass
capacitor, typically 100 pF.
6 5 RF
IN
A Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7 6, 7 AV
DD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AV
DD
has a value of 3 V ± 10%. AV
DD
must have the same voltage as DV
DD
.
8 8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input resistance
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge-pump output into
three-state mode.
11 12 CLOCK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLOCK rising edge. This input is a high impedance CMOS input.
12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs serving as the control bits. This
input is a high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the
five latches. The control bits are used to select the latch.
14 15 MUXOUT
Multiplexer Output. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled
reference frequency to be accessed externally.
15 16, 17 DV
DD
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DV
DD
has a value of 3 V ± 10%. DV
DD
must have the same voltage as AV
DD
.
16 18 V
P
Charge-Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it can
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
EPAD The exposed pad must be connected to ground.
Data Sheet ADF4156
Rev. E | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, I
CP
= 313 μA, phase noise measurements taken on the Agilent E5500
phase noise system.
1
0
–4
0
0
9
05863-017
FR
EQ
U
ENC
Y (
GHz)
POWER (dBm)
5
0
–
5
–10
–15
–2
0
–25
–3
0
–35
1
2
3 4
5 6
7
8
P
=
4
/
5
P
=
8
/
9
Figure 5. RF Input Sensitivity
0
1k
100M
05863-018
FREQUE
NCY (
H
z)
PHASE NOISE (dBc/Hz)
–2
0
–40
–6
0
–80
–100
–120
–140
–160
–180
10
k
100k 1M 10M
L
OW
NOI
SE
M
O
D
E
RF
= 5800.
25
MH
z,
P
FD
= 25
M
Hz
, N
=
232,
FRAC
=
2
,
M
O
D
= 200
, 20k
Hz L
OOP
BW,
I
CP
=
313µA,
DS
B IN
TE
GRA
TE
D
PHA
SE E
RROR = 0.73° RMS,
P
HASE
N
OISE @ 5kHz = –89.5dBc/H
z,
ZCOMM V940ME03 VC
O
Figure 6. Phase Noise and Spurs, Low Noise Mode
0
1k 100M
05863-019
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
–20
–40
–60
–80
–100
–120
–140
–160
–180
10k 100k 1M 10M
LOW SPUR MODE
RF = 5800.25MHz, PFD = 25MHz, N = 232, FRAC = 2,
MOD = 200, 20kHz LOOP BW, I
CP
= 313µA,
DSB INTEGRATED PHASE ERROR = 1.09° RMS,
PHASE NOISE @ 5kHz = –83dBc/Hz, ZCOMM V940ME03 VCO
Figure 7. Phase Noise and Spurs, Low Spur Mode
(Note that Fractional Spurs Are Removed and Only
the Integer Boundary Spur Remains in Low Spur Mode)
6.00
5
.
6
5
–100
900
05863-021
TI
ME
(µ
s
)
FREQUENCY (GHz)
5
.
9
5
5
.
9
0
5
.
8
5
5
.8
0
5
.
7
5
5
.
7
0
0
100
200
30
0 40
0 50
0
600
700
80
0
C
SR
O
FF
C
S
R
O
N
Figure 8. Lock Time for 200 MHz Jump, from 5705 MHz to 5905 MHz,
with CSR On and Off
5.65
5.
6
0
5
.
95
5
.9
0
5.
85
5.
80
5.7
5
5.70
–10
0 900
05863-022
TIME (µs
)
FREQUENCY (GHz)
0 10
0 20
0
300
400
500 600 700
800
C
SR
O
N
CSR
OFF
Figure 9. Lock Time for 200 MHz Jump, from 5905 MHz to 5705 MHz,
with CSR On and Off
V
CP
(V)
6
0
–6
I
CP
(mA)
4
2
–2
–4
–5
–3
–1
1
3
5
0 1 2 3 4 5
05863-020
Figure 10. Charge-Pump Output Characteristics
ADF4156 Data Sheet
Rev. E | Page 8 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. While the
device is operating, SW1 and SW2 are usually closed switches
and SW3 is open. When a power-down is initiated, SW3 is
closed and SW1 and SW2 are opened. This ensures that the
REF
IN
pin is not loaded while the device is powered down.
BUFFER
TO R-COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
05863-005
Figure 11. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
two-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
BI
AS
G
EN
ERA
T
OR
1.6
V
AG
ND
A
V
D
D
RF
IN
B
RF
IN
A
2kΩ
2k
Ω
05863-006
Figure 12. RF Input Stage
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R-counter, enable generating output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the RF
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (RF
OUT
) equation is
RF
OUT
= F
PFD
× (INT + (FRAC/MOD)) (1)
where RF
OUT
is the output frequency of an external voltage-
controlled oscillator (VCO).
F
PFD
= REF
IN
× [(1 + D)/(R × (1 + T))] (2)
where:
REF
IN
is the reference input frequency.
D is the REF
IN
doubler bit.
T is the REF
IN
divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N-DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N-COUNTER
05863-007
Figure 13. RF INT Divider
RF R-COUNTER
The 5-bit RF R-counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 32 are allowed.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

ADF4156BCPZ-RL7

Mfr. #:
Buy ADF4156BCPZ-RL7
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL 6.2 GHz Fractional-N Freq Synthesizer
Lifecycle:
New from this manufacturer.
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