Data Sheet ADF4156
Rev. E | Page 13 of 24
MOD/R REGISTER, R2
With the control bits (Bits[2:0]) of Register R1 set to 010, the
on-chip MOD/R register is programmed. Figure 19 shows the
input data format for programming this register.
Noise and Spur Mode
The noise modes on the ADF4156 are controlled by DB30 and
DB29 in the MOD/R register. See Figure 19 for the truth table.
The noise modes allow the user to optimize a design either for
improved spurious performance or for improved phase noise
performance.
When the lowest spur setting is chosen, dither is enabled. This
randomizes the fractional quantization noise so that it resembles
white noise, rather than spurious noise. As a result, the part is
optimized for improved spurious performance. This operation
is typically used when the PLL closed-loop bandwidth is wide
for fast-locking applications. Wide loop bandwidth is defined as
a loop bandwidth greater than 1/10 of the RF
OUT
channel step
resolution (f
RES
). A wide loop filter does not attenuate the spurs
to the same level as a narrow loop bandwidth.
For best noise performance, use the lowest noise setting option.
As well as disabling the dither, using the lowest noise setting
ensures that the charge pump is operating in an optimum
region for noise performance. This setting is useful if a narrow
loop filter bandwidth is available. The synthesizer ensures
extremely low noise, and the filter attenuates the spurs. The
typical performance characteristics show the trade-offs in a
typical WCDMA setup for various noise and spur settings.
CSR Enable
Setting this bit to 1 enables cycle slip reduction, which can
improve lock times. Note that the signal at the phase frequency
detector (PFD) must have a 50% duty cycle for cycle slip
reduction to work. The charge-pump current setting must also
be set to a minimum value. See the Fast Lock Times section for
more information. Note that CSR cannot be used if the phase
detector polarity is set to negative.
Charge-Pump Current Setting
DB[27:24] set the charge-pump current setting. These bits
should be set to the charge-pump current as indicated by the
loop filter design (see Figure 19).
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RF
IN
to the PFD input.
Operating at CML levels, the prescaler uses the clock from the
RF input stage and divides it down for the counters. The prescaler
is based on a synchronous 4/5 core. When it is set to 4/5, the
maximum RF frequency allowed is 3 GHz. Therefore, when
operating the ADF4156 with frequencies greater than 3 GHz,
the prescaler must be set to 8/9. The prescaler limits the INT
value as follows:
With P = 4/5, N
MIN
= 23
With P = 8/9, N
MIN
= 75
RDIV/2
Setting this bit to 1 inserts a divide-by-2 toggle flip-flop
between the R-counter and PFD, which extends the maximum
REF
IN
input rate.
Reference Doubler
Setting DB20 to 0 feeds the REF
IN
signal directly into the 5-bit
RF R-counter, disabling the doubler. Setting this bit to 1 multiplies
the REF
IN
frequency by a factor of 2 before feeding it into the 5-bit
R-counter. When the doubler is disabled, the REF
IN
falling edge
is the active edge at the PFD input to the fractional synthesizer.
When the doubler is enabled, both the rising and falling edges
of REF
IN
become active edges at the PFD input.
When the doubler is enabled and the lowest spur mode is chosen,
the in-band phase noise performance is sensitive to the REF
IN
duty cycle. The phase noise degradation can be as much as 5 dB
for REF
IN
duty cycles that are outside a 45% to 55% range. The
phase noise is insensitive to the REF
IN
duty cycle when the device
is in the lowest noise mode and when the doubler is disabled.
The maximum allowable REF
IN
frequency when the doubler is
enabled is 30 MHz.
5-Bit R-Counter
The 5-bit R-counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the phase frequency detector (PFD). Division ratios from
1 to 32 are allowed.
12-Bit Interpolator MOD Value
This programmable register sets the fractional modulus, which is
the ratio of the PFD frequency to the channel step resolution on
the RF output. Refer to the RF Synthesizer: A Worked Example
section for more information.
