SRI512 Memory mapping
Doc ID 13263 Rev 5 19/47
4.4 System area
This area is used to modify the settings of the SRI512. It contains 3 registers:
OTP_Lock_Reg, Fixed Chip_ID and ST Reserved. See Figure 18 for a map of this area.
A Write_block command in this area will not erase the previous contents. Selected bits can
thus be set from 1 to 0. All bits previously at 0 remain unchanged. Once all the 32 bits of a
block are at 0, the block is empty and cannot be updated any more.
Figure 18. System area
4.4.1 OTP_Lock_Reg
The 16 bits, b31 to b16, of the System area (block address 255) are used as
OTP_Lock_Reg bits in the SRI512. They control the write access to the 16 blocks 0 to 15 as
follows:
When b16 is at 0, block 0 is write-protected
When b17 is at 0, block 1 is write-protected
When b18 is at 0, block 2 is write-protected
When b19 is at 0, block 3 is write-protected
When b20 is at 0, block 4 is write-protected
When b21 is at 0, block 5 is write-protected
When b22 is at 0, block 6 is write-protected
When b23 is at 0, block 7 is write-protected
When b24 is at 0, block 8 is write-protected
When b25 is at 0, block 9 is write-protected
When b26 is at 0, block 10 is write-protected
When b27 is at 0, block 11 is write-protected
When b28 is at 0, block 12 is write-protected
When b29 is at 0, block 13 is write-protected
When b30 is at 0, block 14 is write-protected
When b31 is at 0, block 15 is write-protected.
The OTP_Lock_Reg bits cannot be erased. Once write-protected, the blocks behave like
ROM blocks and cannot be unprotected. After any modification of the OTP_Lock_Reg bits, it
is necessary to send a Select command with a valid Chip_ID to the SRI512 in order to load
the block write protection into the logic.
Block
Address
255
MSb 32-bit Block LSb
Description
OTP
OTP_Lock_Reg ST Reserved
Fixed Chip_ID
(Option)
ai12374b
0
b31 b16 b15 b14 b8 b7 b0
Memory mapping SRI512
20/47 Doc ID 13263 Rev 5
4.4.2 Fixed Chip_ID (option)
The SRI512 is provided with an anticollision feature based on a random 8-bit Chip_ID. Prior
to selecting an SRI512, an anticollision sequence has to be run to search for the Chip_ID of
the SRI512. This is a very flexible feature, however the searching loop requires time to run.
For some applications, much time could be saved by knowing the value of the SRI512
Chip_ID beforehand, so that the SRI512 can be identified and selected directly without
having to run an anticollision sequence. This is why the SRI512 was designed with an
optional mask setting used to program a fixed 8-bit Chip_ID to bits b
7
to b
0
of the system
area. When the fixed Chip_ID option is used, the random Chip_ID function is disabled.
SRI512 SRI512 operation
Doc ID 13263 Rev 5 21/47
5 SRI512 operation
All commands, data and CRC are transmitted to the SRI512 as 10-bit characters using ASK
modulation. The start bit of the 10 bits, b
0
, is sent first. The command frame received by the
SRI512 at the antenna is demodulated by the 10% ASK demodulator, and decoded by the
internal logic. Prior to any operation, the SRI512 must have been selected by a Select
command. Each frame transmitted to the SRI512 must start with a start of frame, followed
by one or more data characters, two CRC bytes and the final end of frame. When an invalid
frame is decoded by the SRI512 (wrong command or CRC error), the memory does not
return any error code.
When a valid frame is received, the SRI512 may have to return data to the reader. In this
case, data is returned using BPSK encoding, in the form of 10-bit characters framed by an
SOF and an EOF. The transfer is ended by the SRI512 sending the 2 CRC bytes and the
EOF.

SRI512-W4/1GE

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC RFID TRANSP 13.56MHZ DIE
Lifecycle:
New from this manufacturer.
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