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NCP4308QDR2G

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NCP4308
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16
V
DS
=V
CS
V
TH_CS_RESET
–(R
SHIFT_CS
*I
CS
)
V
TH_CS_OFF
–(R
SHIFT_CS
*I
CS
)
V
TH_CS_ON
–(R
SHIFT_CS
*I
CS
)
V
DRV
Min ON−time
t
Min OFF−time
Min t
OFF
timer was
stopped here because
of V
CS
<V
TH_CS_RESET
t
MIN_TON
t
MIN_TOFF
I
SEC
The t
MIN_TON
and t
MIN_TOFF
are adjustable by R
MIN_TON
and R
MIN_TOFF
resistors
Turn−on delay
Turn−off delay
Figure 37. CS Input Comparators Thresholds and Blanking Periods Timing in LLC
V
DS
=V
CS
V
TH_CS_RESET
–(R
SHIFT_CS
*I
CS
)
V
TH_CS_OFF
–(R
SHIFT_CS
*I
CS
)
V
TH_CS_ON
–(R
SHIFT_CS
*I
CS
)
V
DRV
Min ON−time
t
Min OFF−time
t
MIN_TON
t
MIN_TOFF
I
SEC
The t
MIN_TON
and t
MIN_TOFF
are adjustable by R
MIN_TON
and R
MIN_TOFF
resistors
Turn−on delay
Turn−off delay
Min t
OFF
timer was
stopped here because
of V
CS
<V
TH_CS_RESET
Figure 38. CS Input Comparators Thresholds and Blanking Periods Timing in Flyback
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17
If no R
SHIFT_CS
resistor is used, the turn-on, turn-off and
V
TH_CS_RESET
thresholds are fully given by the CS input
specification (please refer to electrical characteristics table).
The CS pin offset current causes a voltage drop that is equal
to:
V
RSHIFT_CS
+ R
SHIFT_CS
*I
CS
(eq. 1)
Final turn−on and turn off thresholds can be then calculated
as:
V
CS_TURN_ON
+ V
TH_CS_ON
*
ǒ
R
SHIFT_CS
*I
CS
Ǔ
(eq. 2)
V
CS_TURN_OFF
+ V
TH_CS_OFF
*
ǒ
R
SHIFT_CS
*I
CS
Ǔ
(eq. 3)
V
CS_RESET
+ V
TH_CS_RESET
*
ǒ
R
SHIFT_CS
*I
CS
Ǔ
(eq. 4)
Note that R
SHIFT_CS
impact on turn-on and V
TH_CS_RESET
thresholds is less critical than its effect on the turn−off
threshold.
It should be noted that when using a SR MOSFET in a
through hole package the parasitic inductance of the
MOSFET package leads (refer to Figure 39) causes a
turn−off current threshold increase. The current that flows
through the SR MOSFET experiences a high Di(t)/Dt that
induces an error voltage on the SR MOSFET leads due to
their parasitic inductance. This error voltage is proportional
to the derivative of the SR MOSFET current; and shifts the
CS input voltage to zero when significant current still flows
through the MOSFET channel. As a result, the SR MOSFET
is turned−off prematurely and the efficiency of the SMPS is
not optimized − refer to Figure 40 for a better understanding.
Figure 39. SR System Connection Including MOSFET and Layout Parasitic Inductances in LLC Application
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18
Figure 40. Waveforms From SR System Implemented in LLC Application and Using MOSFET in TO220 Package
With Long Leads − SR MOSFET channel Conduction Time is Reduced
Note that the efficiency impact caused by the error voltage
due to the parasitic inductance increases with lower
MOSFETs R
DS(on)
and/or higher operating frequency.
It is thus beneficial to minimize SR MOSFET package
leads length in order to maximize application efficiency. The
optimum solution for applications with high secondary
current Di/Dt and high operating frequency is to use
lead−less SR MOSFET i.e. SR MOSFET in SMT package.
The parasitic inductance of a SMT package is negligible
causing insignificant CS turn−off threshold shift and thus
minimum impact to efficiency (refer to Figure 41).
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NCP4308QDR2G

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Buy NCP4308QDR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers SYNCHRONOUS RECTIFIER CON
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