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NCP4308QDR2G

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NCP4308
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19
Figure 41. Waveforms from SR System Implemented in LLC Application and Using MOSFET in SMT Package with
Minimized Parasitic Inductance − SR MOSFET Channel Conduction Time is Optimized
It can be deduced from the above paragraphs on the
induced error voltage and parameter tables that turn−off
threshold precision is quite critical. If we consider a SR
MOSFET with R
DS(on)
of 1 mW, the 1 mV error voltage on
the CS pin results in a 1 A turn-off current threshold
difference; thus the PCB layout is very critical when
implementing the SR system. Note that the CS turn-off
comparator is referred to the GND pin. Any parasitic
impedance (resistive or inductive − even on the magnitude
of mW and nH values) can cause a high error voltage that is
then evaluated by the CS comparator. Ideally the CS
turn−off comparator should detect voltage that is caused by
secondary current directly on the SR MOSFET channel
resistance. In reality there will be small parasitic impedance
on the CS path due to the bonding wires, leads and soldering.
To assure the best efficiency results, a Kelvin connection of
the SR controller to the power circuitry should be
implemented. The GND pin should be connected to the SR
MOSFET source soldering point and current sense pin
should be connected to the SR MOSFET drain soldering
point − refer to Figure 39. Using a Kelvin connection will
avoid any impact of PCB layout parasitic elements on the SR
controller functionality; SR MOSFET parasitic elements
will still play a role in attaining an error voltage. Figure 42
and Figure 43 show examples of SR system layouts using
MOSFETs in TO220 and SMT packages. It is evident that
the MOSFET leads should be as short as possible to
minimize parasitic inductances when using packages with
leads (like TO220). Figure 43 shows how to layout design
with two SR MOSFETs in parallel. It has to be noted that it
is not easy task and designer has to paid lot of attention to do
symmetric Kelvin connection.
Figure 42. Recommended Layout When Using SR
MOSFET in TO220 Package
Figure 43. Recommended Layout When Using SR
MOSFET in SMT Package (2x SO8 FL)
NCP4308
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20
Figure 44. NCP4308 Operation after Start−Up Event
V
DS
= V
CS
V
TH_CS_RESET
V
TH_CS_OFF
V
TH_CS_ON
V
CCON
Min OFF− time
V
DRV
V
CC
Min ON−time
t
MIN_TOFF
t
MIN_TOFF
t
MIN_TON
Not complete
t
MIN_TOFF
−
>
IC
is not activated
Complete
t
MIN_TOFF
activates IC
t
MIN_TOFF
is stopped
due to V
DS
drops
below V
TH_CS_RESET
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
Self Synchronization
Self synchronization feature during start−up can be seen
at Figure 44. Figure 44 shows how the minimum off−time
timer is reset when CS voltage is oscillating through
V
TH_CS_RESET
level. The NCP4308 starts operation at time
t1. Internal logic waits for one complete minimum off−time
period to expire before the NCP4308 can activate the driver
after a start−up event. The minimum off−time timer starts to
run at time t1, because V
CS
is higher than V
TH_CS_RESET
.
The timer is then reset, before its set minimum off−time
period expires, at time t2 thanks to CS voltage lower than
V
TH_CS_RESET
threshold. The aforementioned reset
situation can be seen again at time t3, t4, t5 and t6. A
complete minimum off−time period elapses between times
t7 and t8 allowing the IC to activate a driver output after time
t8.
Minimum t
ON
and t
OFF
Adjustment
The NCP4308 offers an adjustable minimum on−time and
off−time blanking periods that ease the implementation of a
synchronous rectification system in any SMPS topology.
These timers avoid false triggering on the CS input after the
MOSFET is turned on or off.
The adjustment of minimum t
ON
and t
OFF
periods are
done based on an internal timing capacitance and external
resistors connected to the GND pin − refer to Figure 45 for
a better understanding.
NCP4308
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21
Figure 45. Internal Connection of the MIN_TON Generator (the MIN_TOFF Works in the Same Way)
Current through the MIN_TON adjust resistor can be
calculated as:
I
R_MIN_TON
+
V
ref
R
MIN_TON
(eq. 5)
If the internal current mirror creates the same current
through R
MIN_TON
as used the internal timing capacitor (Ct)
charging, then the minimum on−time duration can be
calculated using this equation.
t
MIN_TON
+ C
t
V
ref
I
R_MIN_TON
+ C
t
V
ref
V
ref
R
MIN_TON
+ C
t
@ R
MIN_TO
N
(eq. 6)
The internal capacitor size would be too large if
I
R_MIN_TON
was used. The internal current mirror uses a
proportional current, given by the internal current mirror
ratio. One can then calculate the MIN_TON and
MIN_TOFF blanking periods using below equations:
t
MIN_TON
+ 1.00 * 10
−4
*R
MIN_TON
[ms]
(eq. 7)
t
MIN_TOFF
+ 1.00 * 10
−4
*R
MIN_TOFF
[ms]
(eq. 8)
Note that the internal timing comparator delay affects the
accuracy of Equations 7 and 8 when MIN_TON/
MIN_TOFF times are selected near to their minimum
possible values. Please refer to Figures 46 and 47 for
measured minimum on and off time charts.
Figure 46. MIN_TON Adjust Characteristics
R
MIN_TON
(kW)
906050403020100
0
1
2
4
5
6
7
10
t
MIN_TON
(ms)
100
3
8070
8
9
Figure 47. MIN_TOFF Adjust Characteristics
R
MIN_TOFF
(kW)
906050403020100
0
1
2
4
5
6
7
10
t
MIN_TOFF
(ms)
100
3
8070
8
9
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NCP4308QDR2G

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Buy NCP4308QDR2G
Manufacturer:
ON Semiconductor
Description:
Switching Controllers SYNCHRONOUS RECTIFIER CON
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