IP4856CX25_C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 15 October 2014 12 of 21
NXP Semiconductors
IP4856CX25/C
SD 3.0-compliant memory card integrated dual voltage level translator
12.2 Level translator
[1] Transition between V
OL
= 0.35 V
CCA
and V
OH
= 0.65 V
CCA
.
[2] Transition between V
OL
= 0.45 V and V
OH
= 1.4 V.
Table 12. Level translator dynamic characteristics
At recommended operating conditions; V
CCA
= 1.8 V; T
amb
=25
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Host-side transition times
t
r
rise time SEL = HIGH (1.8 V interface)
[1]
-0.41.0ns
t
f
fall time SEL = HIGH (1.8 V interface)
[1]
-0.41.0ns
Card-side transition times
t
r
rise time SEL = HIGH (1.8 V interface)
[2]
0.40.91.4ns
t
f
fall time SEL = HIGH (1.8 V interface)
[2]
0.40.91.4ns
Host-side to card-side propagation delay
DATAx_H to DATAx_SD, CMD_H to CMD_SD and CLK_IN to CLK_SD
t
pd
propagation delay SEL = HIGH (1.8 V interface) - 2.4 3.5 ns
Host-side to host-side propagation delay
CLK_IN to CLK_FB
t
pd
propagation delay SEL = HIGH (1.8 V interface) - 4.8 7.0 ns
Card-side to host-side propagation delay
DATAx_SD to DATAx_H and CMD_SD to CMD_H
t
pd
propagation delay SEL = HIGH (1.8 V interface) - 2.4 3.5 ns
Fig 6. Output rise and fall times
W
W
DDD
W
W

9
,/
9
,+
9
&&
*1'
 

IP4856CX25_C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 15 October 2014 13 of 21
NXP Semiconductors
IP4856CX25/C
SD 3.0-compliant memory card integrated dual voltage level translator
12.3 ESD characteristic of pin write protect and card detect
[1] TLP according to ANSI-ESD STM5.5.1/IEC 62615 Z
o
=50; pulse width = 100 ns; rise time = 200 ps;
averaging window = 50 ns to 80 ns.
Fig 7. Output delay timing
DDD
RXWSXWGHOD\WLPH
9
2+
9
,+
9
,/
9
&&
&/.B,1
*1'
*1'
9
2+
'$
7$>@B6'
9
&&
9
,/
9
,+
Table 13. ESD characteristic of write protect and card detect
At recommended operating conditions; T
amb
=25
C; voltages are referenced to
GND (ground = 0 V); unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ESD protection pins: WP and CD
V
BR
breakdown voltage TLP; I = 1 mA - 8 - V
r
dyn
dynamic resistance positive transient
[1]
-0.5-
negative transient
[1]
-0.5-
IP4856CX25_C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 15 October 2014 14 of 21
NXP Semiconductors
IP4856CX25/C
SD 3.0-compliant memory card integrated dual voltage level translator
13. Test information
Definitions test circuit:
R
source
= source resistance of pulse generator.
R
term
= termination resistance should be equal to output impedance Z
o
of pulse generator.
C
L
= load capacitance including jig and probe capacitance.
R
L
= load resistance.
Fig 8. Load circuitry for measuring switching time
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SXOVHZLGWK


9
9
,
9
,
QHJDWLYH
LQSXW
SRVLWLYH
LQSXW
9
 


W
IR
W
UR
W
UR
W
IR
DDD
'87
9
&&
9
6833/<
9
,
9
2
5
WHUP
5
VRXUFH
5
/
&
/
38/6(
*(1(5$
725
'87
ȍ
SXOVHZLGWK

IP4856CX25/CZ

Mfr. #:
Manufacturer:
Nexperia
Description:
Translation - Voltage Levels SD 3.0compliant dual voltage level trans
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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