IP4856CX25_C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 2 — 15 October 2014 5 of 21
NXP Semiconductors
IP4856CX25/C
SD 3.0-compliant memory card integrated dual voltage level translator
[1] The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards.
[2] I = input, O = output, I/O = input and output, S = power supply.
8. Functional description
8.1 Level translator
The bidirectional level translator shifts the data between the I/O supply levels of the host
and the memory card. Dedicated direction control signals determine if a command and
data signals are transferred from the memory card to the host (card read mode) or from
the host to the memory card (card write mode). The voltage translator has to support
several clock and data transfer rates at the signaling levels specified in the SD 3.0
standard specification.
CLK_IN C1 I clock signal input on host side
ENABLE C2 I device enable input
GND C3 S supply ground
V
SD_REF
C4 I reference voltage for the internal voltage regulator
CLK_SD C5 O clock signal output on memory card side
DATA0_H D1 I/O data 0 input or output on host side
CMD_H D2 I/O command input or output on host side
CD D3 O card detect switch biasing output
CMD_SD D4 I/O command input or output on memory card side
DATA0_SD D5 I/O data 0 input or output on memory card side
DATA1_H E1 I/O data 1 input or output on host side
CLK_FB E2 O clock feedback output on host side
DIR_1_3 E3 I direction control input for data 1, data 2, data 3
WP E4 O write protect switch biasing output
DATA1_SD E5 I/O data 1 input or output on memory card side
Table 3. Pin description
…continued
Symbol
[1]
Pin Type
[2]
Description
Table 4. Supported modes
Bus speed mode Signal level (V) Clock rate (MHz) Data rate (MB/s)
Default-speed 3.3 25 12.5
High-speed 3.3 50 25
SDR12 1.8 25 12.5
SDR25 1.8 50 25
SDR50 1.8 100 50
SDR104 1.8 208 104
DDR50 1.8 50 50
