EP3SE110F1152C3

© March 2010 Altera Corporation Stratix III Device Handbook, Volume 1

1. Stratix III Device Family Overview

The Stratix

®

III family provides one of the most architecturally advanced,

high-performance, low-power FPGAs in the marketplace.

Stratix III FPGAs lower power consumption through Altera’s innovative

Programmable Power Technology, which provides the ability to turn on the

performance where needed and turn down the power consumption for blocks not in

use. Selectable Core Voltage and the latest in silicon process optimizations are also

efficiency and flexibility to the high-speed I/O. Package and die enhancements with

dynamic on-chip termination, output delay, and current strength control provide

best-in-class signal integrity.

Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a

programmable alternative to custom ASICs and programmable processors for

high-performance logic, digital signal processing (DSP), and embedded designs.

Stratix III devices include optional configuration bit stream security through volatile

or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where

■ 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM

■ High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18,

and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and

finite impulse response (FIR) filters

■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for

robust signal integrity

■ Programmable Power Technology, which minimizes power while maximizing

device performance

SIII51001-1.8

■ Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device

■ Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration,

shifting

■ Memory interface support with dedicated DQS logic on all I/O banks

■ Support for high-speed external memory interfaces including DDR, DDR2,

DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular

I/O banks

■ Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide

range of industry I/O standards

■ The only high-density, high-performance FPGA with support for 256-bit AES

■ Robust on-chip hot socketing and power sequencing support

■ Integrated cyclical redundancy check (CRC) for configuration memory error

■ Built-in error correction coding (ECC) circuitry to detect and correct data errors in

■ Nios

■ Support for multiple intellectual property megafunctions from Altera

address a wide range of applications, while the enhanced family (E) offers more

Total ROM Kbits = Total Embedded RAM Kbits + [(# of MLAB blocks × 640)/1024]

(3) The availability of the PLLs shown in this column is based on the device with the largest package. Refer to the Clock Networks and PLLs in Stratix

III Devices chapter in volume 1 of the Stratix III Device Handbook for the availability of the PLLs for each device.