EP3SE110F1152C3 Datasheet EP3SE50F484C2G, EP3SL70F484I3G, EP3SE50F780I3G | P7-P9

Chapter 1: Stratix III Device Family Overview 1–7

Architecture Features

MultiTrack Interconnect

In the Stratix III architecture, connections between ALMs, TriMatrix memory, DSP

blocks, and device I/O pins are provided by the MultiTrack interconnect structure

with DirectDrive technology. The MultiTrack interconnect consists of continuous,

performance-optimized row and column interconnects that span fixed distances. A

routing structure with fixed length resources for all devices allows predictable and

repeatable performance when migrating through different device densities. The

MultiTrack interconnect provides 1-hop connection to 34 adjacent LABs, 2-hop

connections to 96 adjacent LABs and 3-hop connections to 160 adjacent LABs.

DirectDrive technology is a deterministic routing technology that ensures identical

routing resource usage for any function regardless of placement in the device. The

MultiTrack interconnect and DirectDrive technology simplify the integration stage of

block-based designing by eliminating the reoptimization cycles that typically follow

design changes and additions. The Quartus II Compiler also automatically places

critical design paths on faster interconnects to improve design performance.

f For more information, refer to the MultiTrack Interconnect in Stratix III Devices chapter.

TriMatrix Embedded Memory Blocks

TriMatrix embedded memory blocks provide three different sizes of embedded

SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory

includes the following blocks:

■ 320-bit MLAB blocks optimized to implement filter delay lines, small FIFO buffers,

and shift registers

■ 9-Kbit M9K blocks that can be used for general purpose memory applications

■ 144-Kbit M144K blocks that are ideal for processor code storage, packet and video

frame buffering

Each embedded memory block can be independently configured to be a single- or

dual-port RAM, ROM, or shift register via the Quartus II MegaWizard

Plug-In

Manager. Multiple blocks of the same type can also be stitched together to produce

larger memories with minimal timing penalty. TriMatrix memory provides up to

16,272 Kbits of embedded SRAM at up to 600 MHz operation.

f For more information about TriMatrix memory blocks, modes, features, and design

considerations, refer to the TriMatrix Embedded Memory Blocks in Stratix III Devices

chapter.

DSP Blocks

Stratix III devices have dedicated high-performance digital signal processing (DSP)

blocks optimized for DSP applications requiring high data throughput. Stratix III

devices provide you with the ability to implement various high-performance DSP

functions easily. Complex systems such as WiMAX, 3GPP WCDMA, CDMA2000,

voice over Internet Protocol (VoIP), H.264 video compression, and high-definition

television (HDTV) require high-performance DSP blocks to process data. These

system designs typically use DSP blocks to implement finite impulse response (FIR)

filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier

transform (FFT) functions, and discrete cosine transform (DCT) functions.

1–8 Chapter 1: Stratix III Device Family Overview

Architecture Features

Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation

Stratix III devices have up to 112 DSP blocks. The architectural highlights of the

Stratix III DSP block are the following:

■ High-performance, power optimized, fully pipelined multiplication operations

■ Native support for 9-bit, 12-bit, 18-bit, and 36-bit word lengths

■ Native support for 18-bit complex multiplications

■ Efficient support for floating point arithmetic formats (24-bit for Single Precision

and 53-bit for Double Precision)

■ Signed and unsigned input support

■ Built-in addition, subtraction, and accumulation units to efficiently combine

multiplication results

■ Cascading 18-bit input bus to form tap-delay lines

■ Cascading 44-bit output bus to propagate output results from one block to the next

block

■ Rich and flexible arithmetic rounding and saturation units

■ Efficient barrel shifter support

■ Loopback capability to support adaptive filtering

DSP block multipliers can optionally feed an adder/subtractor or accumulator in the

block depending on user configuration. This option saves ALM routing resources and

increases performance, because all connections and blocks are inside the DSP block.

Additionally, the DSP Block input registers can efficiently implement shift registers

for FIR filter applications, and the Stratix III DSP blocks support rounding and

saturation. The Quartus II software includes megafunctions that control the mode of

operation of the DSP blocks based on user parameter settings.

f For more information, refer to the DSP Blocks in Stratix III Devices chapter.

Clock Networks and PLLs

Stratix III devices provide dedicated Global Clock Networks (GCLKs), Regional Clock

Networks (RCLKs), and Periphery Clock Networks (PCLKs). These clocks are

organized into a hierarchical clock structure that provides up to 104 unique clock

domains (16 GCLK + 88 RCLK) within the Stratix III device and allows for up to 38 (16

GCLK + 22 RCLK) unique GCLK/RCLK clock sources per device quadrant.

Stratix III devices deliver abundant PLL resources with up to 12 PLLs per device and

up to 10 outputs per PLL. Every output can be independently programmed, creating a

unique, customizable clock frequency. Inherent jitter filtration and fine granularity

control over multiply, divide ratios, and dynamic phase-shift reconfiguration provide

the high-performance precision required in today’s high-speed applications. Stratix III

PLLs are feature rich, supporting advanced capabilities such as clock switchover,

reconfigurable phase shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs

can be used for general-purpose clock management supporting multiplication, phase

shifting, and programmable duty cycle. Stratix III PLLs also support external

feedback mode, spread-spectrum input clock tracking, and post-scale counter

cascading.

Chapter 1: Stratix III Device Family Overview 1–9

Architecture Features

f For more information, refer to the Clock Networks and PLLs in Stratix III Devices

chapter.

I/O Banks and I/O Structure

Stratix III devices contain up to 24 modular I/O banks, each of which contains 24, 32,

36, 40, or 48 I/Os. This modular bank structure improves pin efficiency and eases

device migration. The I/O banks contain circuitry to support external memory

interfaces at speeds up to 533 MHz and high-speed differential I/O interfaces meeting

up to 1.6 Gbps performance. It also supports high-speed differential inputs and

outputs running at speeds up to 800 MHz.

Stratix III devices support a wide range of industry I/O standards, including

single-ended, voltage referenced single-ended, and differential I/O standards. The

Stratix III I/O supports programmable bus hold, programmable pull-up resistor,

programmable slew rate, programmable drive strength, programmable output delay

control, and open-drain output. Stratix III devices also support on-chip series (R

) and

on-chip parallel (R

) termination with auto calibration for single-ended I/O standards

and on-chip differential termination (R

) for LVDS I/O standards on Left/Right I/O

banks. Dynamic OCT is also supported on bi-directional I/O pins in all I/O banks.

f For more information, refer to the Stratix III Device I/O Features chapter.

External Memory Interfaces

The Stratix III I/O structure has been completely redesigned to provide flexibility and

enable high-performance support for existing and emerging external memory

standards such as DDR, DDR2, DDR3, QDR II, QDR II+, and RLDRAM II at

frequencies of up to 533 MHz.

Packed with features such as dynamic on-chip termination, trace mismatch

compensation, read/write leveling, half-rate registers, and 4-to 36-bit programmable

DQ group widths, Stratix III I/Os supply the built-in functionality required for rapid

and robust implementation of external memory interfaces. Double data-rate support

is found on all sides of the Stratix III device. Stratix III devices provide an efficient

architecture to quickly and easily fit wide external memory interfaces exactly where

you want them.

A self-calibrating soft IP core (ALTMEMPHY), optimized to take advantage of the

Stratix III device I/O, along with the Quartus II timing analysis tool (TimeQuest),

provide the total solution for the highest reliable frequency of operation across

process voltage and temperature.

f For more information about external memory interfaces, refer to the External Memory

Interfaces in Stratix III Devices chapter.

High-Speed Differential I/O Interfaces with DPA

Stratix III devices contain dedicated circuitry for supporting differential standards at

speeds up to 1.6 Gbps. The high-speed differential I/O circuitry supports the

following high-speed I/O interconnect standards and applications: Utopia IV, SPI-4.2,

SFI-4, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI. Stratix III devices support 2×,

4×, 6×, 7×, 8×, and 10× SERDES modes for high-speed differential I/O interfaces and

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

EP3SE110F1152C3

Mfr. #:

Buy EP3SE110F1152C3

Manufacturer:

Intel / Altera

Description:

FPGA - Field Programmable Gate Array FPGA - Stratix III 4300 LABs 744 IOs

Lifecycle:

New from this manufacturer.

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EP3SE110F1152C3

EP3SE110F1152C3

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