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EP3SE110F1152C3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Chapter 1: Stratix III Device Family Overview 1–13
Reference and Ordering Information
© March 2010 Altera Corporation Stratix III Device Handbook, Volume 1
Signal Integrity
Stratix III devices simplify the challenge of signal integrity through a number of chip,
package, and board level enhancements to enable efficient high-speed data transfer
into and out of the device. These enhancements include:
■ 8:1:1 user I/O/Gnd/V
CC
ratio to reduce the loop inductance in the package
■ Dedicated power supply for each I/O bank, limit of I/Os is 24 to 48 I/Os per bank,
to help limit simultaneous switching noise
■ Programmable slew-rate support with up to four settings to match desired I/O
standard, control noise, and overshoot
■ Programmable output-current drive strength support with up to six settings to
match desired I/O standard performance
■ Programmable output-delay support to control rise/fall times and adjust duty
cycle, compensate for skew, and reduce simultaneous switching outputs (SSO)
noise
■ Dynamic OCT with auto calibration support for series and parallel OCT and
differential OCT support for LVDS I/O standard on the left/right banks
f For more information about SI support in the Quartus II software, refer to the
Quartus II Handbook.
f For more information about how to use the various configuration, PLL, external
memory interfaces, I/O, high-speed differential I/O, power, and JTAG pins, refer to
the Stratix III Device Family Pin Connection Guidelines.
Reference and Ordering Information
The following section describes Stratix III device software support and ordering
information.
Software Support
Stratix III devices are supported by the Altera Quartus II design software, version 6.1
and later, which provides a comprehensive environment for
system-on-a-programmable-chip (SOPC) design. The Quartus II software includes
HDL and schematic design entry, compilation and logic synthesis, full simulation and
advanced timing analysis, SignalTap
®
II logic analyzer, and device configuration.
f For more information about the Quartus II software features, refer to the Quartus II
Handbook.
The Quartus II software supports a variety of operating systems. The specific
operating system for the Quartus II software can be obtained from the Quartus II
Readme.txt file or the Operating System Support section of the Altera website. It also
supports seamless integration with industry-leading EDA tools through the
NativeLink
®
interface.
1–14 Chapter 1: Stratix III Device Family Overview
Chapter Revision History
Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation
Ordering Information
Figure 1–1 shows the ordering codes for Stratix III devices.
f For more information about a specific package, refer to the Stratix III Device Package
Information chapter.
Chapter Revision History
Tab le 1 –6 lists the revision history for this chapter.
Figure 1–1. Stratix III Device Packaging Ordering Information
Device Type
Package Type
2, 3, or 4, with 2 being the fastest
Number of p ins for a part icular p ackage:
F:
FineLine BGA (FBGA)
EP3SL:
EP3SE:
Stratix III Logic
Stratix III DSP/Memory
50
70
80
110
150
200
260
340
C: Commercial temperature (t
J
= 0 C to 85 C)
Indust rial t emperat ure (t
J
= -40 C to 100 C)
Optional SuffixFa m i l y S i g n a t u r e
Operating Temperature
Sp e e d Gr a d e
Pi n Count
2EP3SL 150
C
1152
F
ES
Indicates specific device options
N: Lead-free devices
I:
484
1152
1517
780
1760
L: Low-voltage devices
ES: Engineering sample
H:
Hybrid FineLine BGA (HBGA)
Table 1–6. Chapter Revision History (Part 1 of 2)
Date Version Changes Made
March 2010 1.8
Updated for the Quartus II software version 9.1 SP2 release:
■ Updated Table 1–2.
■ Updated “I/O Banks and I/O Structure” section.
May 2009 1.7 Updated “Software” and “Signal Integrity” sections.
February 2009 1.6
■ Updated “Features” section.
■ Updated Table 1–1.
■ Removed “Referenced Documents” section.
October 2008 1.5
■ Updated “Features” section.
■ Updated Table 1–1 and Table 1–5.
■ Updated New Document Format.
Chapter 1: Stratix III Device Family Overview 1–15
Chapter Revision History
© March 2010 Altera Corporation Stratix III Device Handbook, Volume 1
May 2008 1.4
■ Updated “Introduction”.
■ Updated Table 1–1.
■ Updated Table 1–2.
■ Added Table 1–5.
■ Updated “Reference and Ordering Information”.
■ Updated package type information in Figure 1–1.
November 2007 1.3
■ Updated Table 1–1.
■ Updated Table 1–2.
October 2007 1.2
■ Minor typo fixes.
■ Added Table 1–4.
■ Added section “Referenced Documents”.
■ Added live links for references.
May 2007 1.1
Minor formatting changes, fixed PLL numbers and ALM, LE and MLAB bit counts in
Table 1–1.
November 2006 1.0 Initial Release.
Table 1–6. Chapter Revision History (Part 2 of 2)
Date Version Changes Made
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

EP3SE110F1152C3

Mfr. #:
Buy EP3SE110F1152C3
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array FPGA - Stratix III 4300 LABs 744 IOs
Lifecycle:
New from this manufacturer.
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