EP3SE110F1152C3 Datasheet EP3SE50F484C2G, EP3SL70F484I3G, EP3SE50F780I3G | P10-P12

1–10 Chapter 1: Stratix III Device Family Overview

Architecture Features

Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation

4×, 6×, 7×, 8×, and 10× SERDES modes when using the dedicated DPA circuitry. DPA

minimizes bit errors, simplifies PCB layout and timing management for high-speed

data transfer, and eliminates channel-to-channel and channel-to-clock skew in

high-speed data transmission systems. Soft CDR can also be implemented, enabling

low-cost 1.6-Gbps clock embedded serial links.

Stratix III devices have the following dedicated circuitry for high-speed differential

I/O support:

■ Differential I/O buffer

■ Transmitter serializer

■ Receiver deserializer

■ Data realignment

■ Dynamic phase aligner (DPA)

■ Soft CDR functionality

■ Synchronizer (FIFO buffer)

■ PLLs

f For more information, refer to the High Speed Differential I/O Interfaces with DPA in

Stratix III Devices chapter.

Hot Socketing and Power-On Reset

Stratix III devices are hot-socketing compliant. Hot socketing is also known as hot

plug-in or hot swap, and power sequencing support without the use of any external

devices. Robust on-chip hot-socketing and power-sequencing support ensures proper

device operation independent of the power-up sequence. You can insert or remove a

Stratix III board in a system during system operation without causing undesirable

effects to the running system bus or the board that was inserted into the system.

The hot-socketing feature makes it easier to use Stratix III devices on PCBs that also

contain a mixture of 3.3-V, 3.0-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. With the

Stratix III hot socketing feature, you do not need to ensure a specific power-up

sequence for each device on the board.

f For more information, refer to the Hot Socketing and Power-On Reset in Stratix III

Devices chapter.

Configuration

Stratix III devices are configured using one of the following four configuration

schemes:

■ Fast passive parallel (FPP)

■ Fast active serial (AS)

■ Passive serial (PS)

■ Joint Test Action Group (JTAG)

All configuration schemes use either an external controller (for example, a MAX

device or microprocessor), a configuration device, or a download cable.

Chapter 1: Stratix III Device Family Overview 1–11

Architecture Features

Stratix III devices support configuration data decompression, which saves

configuration memory space and time. This feature allows you to store compressed

configuration data in configuration devices or other memory and transmit this

compressed bitstream to Stratix III devices. During configuration, the Stratix III

device decompresses the bitstream in real time and programs its SRAM cells.

Stratix III devices support decompression in the FPP when using a MAX II

device/microprocessor plus flash, fast AS, and PS configuration schemes. The

Stratix III decompression feature is not available in the FPP when using the enhanced

configuration device and JTAG configuration schemes.

f For more information, refer to the Configuring Stratix III Devices chapter.

Remote System Upgrades

Stratix III devices feature remote system upgrade capability, allowing error-free

deployment of system upgrades from a remote location securely and reliably. Soft

logic (either the Nios embedded processor or user logic) implemented in a Stratix III

device can download a new configuration image from a remote location, store it in

configuration memory, and direct the dedicated remote system upgrade circuitry to

initiate a reconfiguration cycle. The dedicated circuitry performs error detection

during and after the configuration process, and can recover from an error condition

by reverting back to a safe configuration image, and provides error status

information. This dedicated remote system upgrade circuitry is unique to Stratix

series FPGAs and helps to avoid system downtime.

f For more information, refer to the Remote System Upgrades with Stratix III Devices

chapter.

IEEE 1149.1 (JTAG) Boundary-Scan Testing

Stratix III devices support the JTAG IEEE Std. 1149.1 specification. The Boundary-Scan

Test (BST) architecture offers the capability to test pin connections without using

physical test probes and capture functional data while a device is operating normally.

Boundary-scan cells in the Stratix III device can force signals onto pins or capture data

from pin or logic array signals. Forced test data is serially shifted into the

boundary-scan cells. Captured data is serially shifted out and externally compared to

expected results. In addition to BST, you can use the IEEE Std. 1149.1 controller for

Stratix III device in-circuit reconfiguration (ICR).

f For more information, refer to the IEEE 1149.1 (JTAG) Boundary Scan Testing in

Stratix III Devices chapter.

Design Security

Stratix III devices are high-density, high-performance FPGAs with support for 256-bit

volatile and non-volatile security keys to protect designs against copying, reverse

engineering, and tampering. Stratix III devices have the ability to decrypt a

configuration bitstream using the Advanced Encryption Standard (AES) algorithm,

an industry standard encryption algorithm that is FIPS-197 certified and requires a

256-bit security key.

1–12 Chapter 1: Stratix III Device Family Overview

Architecture Features

Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation

The design security feature is available when configuring Stratix III FPGAs using the

fast passive parallel (FPP) configuration mode with an external host (such as a MAX II

device or microprocessor), or when using fast active serial (AS) or passive serial (PS)

configuration schemes.

f For more information about the design security feature, refer to the Design Security in

Stratix III Devices chapter.

SEU Mitigation

Stratix III devices have built-in error detection circuitry to detect data corruption due

to soft errors in the configuration random-access memory (CRAM) cells. This feature

allows all CRAM contents to be read and verified continuously during user mode

operation to match a configuration-computed CRC value. The enhanced CRC circuit

and frame-based configuration architecture allows detection and location of multiple,

single, and adjacent bit errors which, in conjunction with a soft circuit supplied as a

reference design, allows don’t-care soft errors in the CRAM to be ignored during

device operation. This provides a steep decrease in the effective soft error rate,

increasing system reliability.

On-chip memory block SEU mitigation is also offered using the ninth bit and a

configurable megafunction in the Quartus II software for MLAB and M9K blocks

while the M144K memory blocks have built-in error correction code (ECC) circuitry.

f For more information about the dedicated error detection circuitry, refer to the SEU

Mitigation in Stratix III Devices chapter.

Programmable Power

Stratix III delivers Programmable Power, the only FPGA with user programmable

power options balancing today’s power and performance requirements. Stratix III

devices utilize the most advanced power-saving techniques, including a variety of

process, circuit, and architecture optimizations and innovations. In addition, user

controllable power reduction techniques provide an optimal balance of performance

and power reduction specific for each design configured into the Stratix III FPGA. The

Quartus II software (starting from version 6.1) automatically optimizes designs to

meet the performance goals while simultaneously leveraging the programmable

power-saving options available in the Stratix III FPGA without the need for any

changes to the design flow.

f For more information about Programmable Power in Stratix III devices, refer to the

following documents:

■ Programmable Power and Temperature Sensing Diode in Stratix III Devices chapter

■ AN 437: Power Optimization in Stratix III FPGAs

■ Stratix III Programmable Power White Paper

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

EP3SE110F1152C3

Mfr. #:

Buy EP3SE110F1152C3

Manufacturer:

Intel / Altera

Description:

FPGA - Field Programmable Gate Array FPGA - Stratix III 4300 LABs 744 IOs

Lifecycle:

New from this manufacturer.

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EP3SE110F1152C3

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