BGA3031 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 20 November 2014 6 of 23
NXP Semiconductors
BGA3031
DOCSIS 3.0 plus upstream amplifier
8.2 Register settings
8.2.1 Register address
Only addresses 0000 and 0001 are used. Using any other addresses will not affect the
VGA.
8.2.2 Gain/attenuator setting
The gain shall be controlled via the 3-wire bus. Data bits D0 through D5 set the
gain/attenuator level, with 111111 being the min attenuation setting, and 000101 being the
max attenuation setting. A new gain/attenuator setting can be loaded while the VGA is on
(transmit-enable), but shall not take effect until transmit-enable transitions from LOW to
HIGH.
[1] With every increment of the gain setting between 000110 (6) and 111111 (63) the typical gain will increase
accordingly.
8.2.3 Output stage current setting
The current (of the output stage) shall be controlled via the 3-wire bus. Data bits D6 and
D7 set the current. Setting 11 will set the maximum current for maximum linearity. The
current can be lowered for improved efficiency at lower output power levels, or lower
linearity requirements. Setting 00 will set the minimum current. A new current setting can
be loaded while the VGA is on (transmit-enable), but shall not take effect until
transmit-enable transitions from LOW to HIGH.
The current is automatically reduced at lower gain settings while preserving the linearity
performance.
Table 6. Gain settings
Gain setting G[5:0] Typical gain
binary notation decimal notation (dB)
000000 to 000101 0 to 5 24
000110
[1]
6
[1]
23
111110
[1]
62
[1]
33
111111
[1]
63
[1]
34
Table 7. Supply current settings
At gain setting 63.
Current setting C[1:0] Typical supply current
binary notation decimal notation (mA)
00 0 215
01 1 260
10 2 290
11 3 325
