16
FN6618.3
May 5, 2011
Event Detection Register (EVIC)
EVENT OUTPUT IN BATTERY MODE ENABLE BIT
(EVBATB)
This bit enables/disables the EVDET
pin during battery
backup mode (i.e. VBAT pin supply ON). When the EVBATB
is set to “1”, the Event Detect Output is disabled in battery
backup mode. When the EVBATB is cleared to “0”, the Event
Detect output is enabled in battery backup mode. This
feature can be used to save power during battery mode.
EVENT OUTPUT PULSE MODE (EVIM)
This bit controls the EVDET
pin output mode. With EVIM = 0,
the output is in normal mode and when an event is triggered,
the output will be set LOW until reset. With EVIM = 1, the
output is in pulse mode and when an event is triggered, the
device will generate a 200ms to 300ms pulse at the EVDET
output.
EVENT DETECT ENABLE (EVEN)
This bit enables/disables the Event Detect function of the
ISL12032. When this bit is set to “1”, the Event Detect is
active. When this bit is cleared to “0”, the Event Detect is
disabled.
EVENT TIME-BASED HYSTERESIS (EHYS1, EHYS0)
These bits set the amount of time-based hysteresis that is
present at the EVIN pin for deglitching the input signal. The
settings vary from 0ms (hysteresis OFF) to 31.25ms (delay
of 31.25ms to check for change of state at the EVIN pin).
The Hysteresis function and the Event Input Sampling
function work independently.
EVENT INPUT SAMPLING RATE (ESMP)
These bits set the frequency of sampling of the Event Input
(EVIN). The settings include from 1/4Hz (one sample per 4s)
to 2Hz (twice a second), 1Hz, or continuous sampling
(Always ON). The less frequent the sampling, the lower the
current drain, which can affect battery current drain and
battery life.
.
Event Index Register (EVIX)
The Event Index Register provides the index for locating an
individual event that has been stored. The Event recording
function allows recalling up to 4 events, although the Event
counting register will count up to 255 events. The 0th
location corresponds to the first event, and the 1st through
3rd locations correspond to the most recent events, with the
3rd location (11b) representing the latest event. Therefore,
setting EVIX to 03h location and reading the TSEVT section
will access the timestamp information for the most recent
(latest) event. Setting this register to another value will allow
reading the corresponding event from the TSEVT section.
EVENT BIT (EVIX <1:0>)
These bits are the Event Counter Register index bits. EVIX1
is the MSB and EVIX0 is the LSB.
Trickle Charge Register (TRICK)
The trickle charge function allows charging current to flow
from the V
DD
supply to the VBAT pin through a selectable
current limiting resistor. Disabling the trickle charge function
removes this connection and isolates the battery from the
V
DD
supply in the case charging is not necessary or harmful
(as in the case with a lithium coin cell battery). Note that
there is no charging diode in series with the trickle charge
resistor, but a switch network that adds a small series
resistance to the charging resistance.
TRICKLE CHARGE BIT (TRKEN)
This bit enables/disables the trickle charge capability for the
backup battery supply. Setting this bit to “1” will enable the
trickle charge. Resetting this bit to “0” will disable the trickle
charge function and isolate the battery from the V
DD
supply.
TRICKLE CHARGE RESISTOR (TRKRO<1:0>)
These bits allow the user to change the trickle charge
resistor settings according to the maximum current desired
for the battery or super capacitor charging.
TABLE 9. EVENT DETECTION REGISTER (EVIC)
ADDR 7 6 5 4 3 2 1 0
0Eh X EVBATB EVIM EVEN EHYS1 EHYS0 ESMP1 ESMP0
TABLE 10. EVENT TIME-BASED HYSTERESIS
EHSYS1 EHSYS0 TIME (ms)
00 0
013.9
1 0 16.625
1 1 31.25
TABLE 11. EVENT INPUT SAMPLING RATE
ESMP1 ESMP2 SAMPLING RATE
00 Always ON
01 2 Hz
10 1 Hz
1 1 1/4 Hz
TABLE 12. EVENT INDEX REGISTER (EVIX)
ADDR 7 6 5 4 3 2 1 0
0Fh X X X X X X EVIX1 EVIX0
TABLE 13. TRICKLE CHARGE REGISTER (TRICK)
ADDR 7 6 5 4 3 2 1 0
10h X X X X X TRKEN TRKRO1 TRKRO0
ISL12032
17
FN6618.3
May 5, 2011
Where the R
OUT
is the selected resistor between V
DD
and
VBAT. Table 14 gives the typical resistor values for V
DD
= 5V
and VBAT = 3.0V.
Note that the resistor value changes with
V
DD
input voltage and VBAT voltage, as well as with
temperature.
Power Supply Control Register (PWRVDD)
CLEAR TIME STAMP BIT (CLRTS)
This bit clears both the Time Stamp V
DD
to Battery (TSV2B)
and Time Stamp Battery to V
DD
(TSB2V) sections. The
default setting is “0” which allows normal operation. Setting
CLRTS = 1 performs the clear timestamp register function at
the conclusion of a successful write operation.
I
2
C IN BATTERY MODE (I2CBAT)
This bit allows I
2
C operation in battery backup mode (VBAT
powered) when set to “1”. When reset to “0”, the I
2
C
operation is disabled in battery mode, which results in the
lowest I
DD
current.
Note that when the I
2
C operation is desired in VBAT mode,
the SCL and SDA pull-ups must go to the VBAT source for
proper communications. This will result in additional VBAT
current drain (on top of the increased device VBAT current)
during serial communications.
V
DD
BROWNOUT TRIP VOLTAGE (VDDTRIP <2:0>)
These bits set the 6 trip levels for the V
DD
alarm and VBAT
switchover. The LVDD bit in the SRDC is set to “1” when
V
DD
drops below this preset level. See Table 16.
Battery Voltage Warning Register (PWRVBAT)
This register controls the trip points for the two VBAT
warnings, with levels set to approximately 85% and 75% of
the nominal battery level.
VBAT HYSTERESIS (BHYS)
This bit enables/disables the hysteresis voltage for the
V
DD
/VBAT switchover. When set to “1”, hysteresis is enabled
and switching to VBAT occurs at approximately 50mV below
the V
DD
Trip point (set by VDDTrip<2:0>). Switching from
VBAT to V
DD
power will occur at approximately 50mV above
the V
DD
trip point.
When set to “0”, there is no hysteresis and switchover will
occur at exactly the VDD trip point. Note that for slow moving
V
DD
power-down and power-up signals there can be some
extra switching cycles without hysteresis.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>)
Three bits selects the first alarm (85% of Nominal VBAT) level
for the battery voltage monitor. There are total of 7 levels that
could be selected for the first warning. Any of the levels could
be selected as the first warning with no reference as to nominal
VBAT voltage level. See Table 18 for typical values.
TABLE 14. RESISTOR SELECTION REGISTER
TRKRO1 TRKRO0 Rtrk UNITS
0 0 1300
0 1 2200
1 0 3600
1 1 7800
TABLE 15. POWER SUPPLY CONTROL REGISTER (PWRVDD)
ADDR 7 6 5 4 3 2 1 0
11h CLRTS X I2CBAT LVENB X VDD
Trip2
VDD
Trip1
VDD
Trip0
TABLE 16. VDD TRIP LEVELS
V
DD
Trip2 V
DD
Trip1 V
DD
Trip0
TRIP
VOLTAGE
(V)
0 0 0 2.295
0 0 1 2.550
0 1 0 2.805
I
MAX
V
DD
V
BAT
R
OUT
---------------------------------
=
(EQ. 1)
0 1 1 3.060
1 0 0 4.250
1 0 1 4.675
TABLE 17. BATTERY VOLTAGE WARNING REGISTER
(PWRVBAT)
ADDR 7 6 5 4 3 2 1 0
12h X BHYS VB85T
p2
VB85T
p1
VB85T
p0
VB75T
p2
VB75T
p1
VB75T
p0
TABLE 16. VDD TRIP LEVELS
V
DD
Trip2 V
DD
Trip1 V
DD
Trip0
TRIP
VOLTAGE
(V)
ISL12032
18
FN6618.3
May 5, 2011
BATTERY LEVEL MONITOR TRIP BITS (VB75TP <2:0>)
Three bits selects the second warning (75% of Nominal VBAT)
level for the battery voltage monitor. There are total of 7 levels
that could be selected for the second monitor. Any of the levels
could be selected as the second alarm with no reference as to
nominal VBAT voltage level. See Table 19 for typical values.
AC Register (AC)
This register sets the performance screening for the AC
input.
AC 50/60HZ INPUT SELECT (AC5060)
This bit selects either 50Hz or 60Hz powerline AC clock
input frequency. Setting this bit to “0” selects a 60Hz input
(default). Setting this bit to “1” selects a 50Hz input.
AC ENABLE (ACENB)
This bit will enable/disable the AC clock input. Setting this bit
to “0” will enable the AC clock input (default). Setting this bit
to “1” will disable the AC clock input. When the AC input is
disabled, the crystal oscillator becomes the sole source for
RTC and F
OUT
clocking.
AC RECOVERY PERIOD (ACRP<1:0>)
This bit sets the AC clock input validation recovery period.
After the AC input fails validation (ACFAIL = 1), a predefined
period is used to test the frequency and voltage of the AC
clock input. The range is from 2s to 16s.
AC FAILURE CYCLES (ACFP<1:0>)
These two bits determine how many AC cycles are used for
the AC clock qualification, or to disable the AC clock
qualification. The range is from 1 AC cycle to 12 AC cycles
or disable, and is also dependent on the AC5060 bit setting
(see Table 22). The qualification logic will count the number
of crystal cycles in the chosen AC period, and if the count is
outside the window set by ACFC bits then the ACFAIL signal
is set to “1”.
For example, if 10 cycles are chosen for 50Hz input, then
during those 10 cycles there would need to be exactly 6554
crystal cycles. That number is subtracted from the actual
count during the 10 AC cycles and the absolute value is
compared to the error value set by ACFC. If the error were
10 crystal cycles and ACFC were set to 11b, then the
allowable error would be 20 crystal cycles and the ACFAIL
would be “0”, or qualification has passed. If the actual error
count were 22 cycles then the ACFAIL would be set to “1”,
qualification has failed.
.
AC/CRYSTAL FREQUENCY FAILURE CRITERION
(ACFC<1:0>)
These two bits determine the number of crystal cycles used
for the error budget for the AC qualification (see Table 24).
Two of the choices are for a fixed ppm criterion of 1 or 2
crystal cycles in just one AC cycle (independent of the ACFP
setting). The other choices are for 1 or 2 crystal cycles per
AC cycle, but includes the total number of cycles set by the
ACFP.
Using the example given for the ACFP bits previously
mentioned:
AC5060 = 1 (50Hz)
ACFC = 11b (2 crystal cycles/AC cycle)
TABLE 18. VB85T VBAT WARNING LEVELS
VB85Tp2 VB85Tp1 VB85Tp0
BATTERY
ALARM TRIP
LEVEL (V)
0 0 0 2.125
0 0 1 2.295
0 1 0 2.550
0 1 1 2.805
1 0 0 3.060
1 0 1 4.250
1 1 0 4.675
TABLE 19. VB75T VBAT WARNING LEVELS
VB75Tp2 VB75Tp1 VB75Tp0
BATTERY
ALARM TRIP
LEVEL (V)
0 0 0 1.875
0 0 1 2.025
0 1 0 2.250
0 1 1 2.475
1 0 0 2.700
1 0 1 3.750
1 1 0 4.125
TABLE 20. AC REGISTER
ADDR 7 6 5 4 3 2 1 0
13h AC5060 ACENB ACRP1 ACRP0 ACFP1 ACFP0 ACFC1 ACFC0
TABLE 21. AC RECOVERY PERIOD
ACRP1 ACRP0 RECOVERY TIME
002s
014s
108s
1 1 16s
TABLE 22. AC FAILURE CYCLES
CYCLE USED for COUNT
ACFP1 ACFP0AC5060 = 0 AC5060=1
(Disabled) 0 0
1101
6510
12 10 1 1
ISL12032

ISL12032IVZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock REAL TIME CLK W/ EEPROM 14LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet