ISL12032IVZ Datasheet ISL12032IVZ-T, ISL12032IVZ | P22-P24

FN6618.3

May 5, 2011

Protocol Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (see

Figure 6). On power-up of the ISL12032, the SDA pin is in

the input mode.

All I

C interface operations must begin with a START

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL12032 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (see

Figure 6). A START condition is ignored during the power-up

sequence.

All I

C interface operations must be terminated by a STOP

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (see Figure 6). A STOP condition at the end of

a read operation or at the end of a write operation to memory

only places the device in its standby mode.

An acknowledge (ACK) is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (see Figure 7).

The ISL12032 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL12032 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation.

FIGURE 6. VALID DATA CHANGES, START AND STOP CONDITIONS

FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER

FIGURE 8. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)

SDA

SCL

START

DATA DATA

STOP

STABLE CHANGE

DATA

STABLE

SDA OUTPUT FROM

TRANSMITTER

SDA OUTPUT FROM

RECEIVER

81 9

START ACK

SCL FROM

MASTER

HIGH IMPEDANCE

IDENTIFICATION

BYTE

DATA

BYTE

SIGNALS FROM

THE MASTER

SIGNALS FROM

THE ISL12032

10011

WRITE

SIGNAL AT SDA

0000111

ADDRESS

BYTE

ISL12032

FN6618.3

May 5, 2011

Device Addressing

Following a start condition, the master must output a Slave

Address Byte. The 7 MSBs are the device identifier. These bits

are “1101111b” for the RTC registers and “1010111b” for the

User SRAM.

The last bit of the Slave Address Byte defines a read or write

operation to be performed. When this R/W

bit is a “1”, then a

read operation is selected. A “0” selects a write operation

(refer to Figure 9).

After loading the entire Slave Address Byte from the SDA bus,

the ISL12032 compares the device identifier and device select

bits with “1101111b” or “1010111b”. Upon a correct compare,

the device outputs an acknowledge on the SDA line.

Following the Slave Byte is a one byte word address. The word

address is either supplied by the master device or obtained

from an internal counter. On power up the internal address

counter is set to address 00h, so a current address read starts

at address 00h. When required, as part of a random read, the

master must supply the 1 Word Address Byte as shown in

Figure 9.

In a random read operation, the slave byte in the “dummy write”

portion must match the slave byte in the “read” section. For a

random read of the Control/Status Registers, the slave byte

must be “1101111x” in both places.

Write Operation

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte,

and a STOP condition. After each of the three bytes, the

ISL12032 responds with an ACK. At this time, the I

interface enters a standby state.

A multiple byte operation within a page is permitted. The

Address Byte must have the start address, and the data

bytes are sent in sequence after the address byte, with the

ISL12032 sending an ACK after each byte. The page write is

terminated with a STOP condition from the master. The

pages within the ISL12032 do not support wrapping around

for page read or write operations.

Read Operation

A Read operation consists of a three byte instruction

followed by one or more Data Bytes (see Figure 10). The

master initiates the operation issuing the following

sequence: a START, the Identification byte with the RW

bit

set to “0”, an Address Byte, a second START, and a second

Identification byte with the RW

bit set to “1”. After each of the

three bytes, the ISL12032 responds with an ACK. Then the

ISL12032 transmits Data Bytes as long as the master

responds with an ACK during the SCL cycle following the

eighth bit of each byte. The master terminates the read

operation (issuing a STOP condition) following the last bit of

the last Data Byte (see Figure 10).

The Data Bytes are from the memory location indicated by

an internal pointer. This pointers initial value is determined

by the Address Byte in the Read operation instruction, and

increments by one during transmission of each Data Byte.

After reaching the last memory location in a section or page,

the master should issue a STOP. Bytes that are read at

addresses higher than the last address in a section may be

erroneous.

FIGURE 9. SLAVE ADDRESS, WORD ADDRESS, AND DATA

BYTES

SLAVE

ADDRESS BYTE

D7 D6 D5 D2D4 D3 D1 D0

A0A7 A2A4 A3 A1

DATA BYTE

A6 A5

R/W

WORD ADDRESS

SIGNALS

FROM THE

MASTER

SIGNALS FROM

THE SLAVE

SIGNAL AT

SDA

IDENTIFICATION

BYTE WITH

R/W

ADDRESS

BYTE

IDENTIFICATION

BYTE WITH

R/W

= 1

LAST READ

DATA BYTE

FIRST READ

DATA BYTE

101 1111

101

FIGURE 10. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)

ISL12032

FN6618.3

May 5, 2011

Application Section

Oscillator Crystal Requirements

The ISL12032 uses a standard 32.768kHz crystal. Either

through hole or surface mount crystals can be used.

Table 28 lists some recommended surface mount crystals

and the parameters of each. This list is not exhaustive and

other surface mount devices can be used with the ISL12032

if their specifications are very similar to the devices listed.

The crystal should have a required parallel load capacitance

of 12.5pF and an equivalent series resistance of less than

50k. The crystal’s temperature range specification should

match the application. Many crystals are rated for -10°C to

+60°C (especially through hole and tuning fork types), so an

appropriate crystal should be selected if extended

temperature range is required.

Layout Considerations

The crystal input at X1 has a very high impedance, and

oscillator circuits operating at low frequencies (such as

32.768kHz) are known to pick up noise very easily if layout

precautions are not followed. Most instances of erratic

clocking or large accuracy errors can be traced to the

susceptibility of the oscillator circuit to interference from

adjacent high speed clock or data lines. Careful layout of the

RTC circuit will avoid noise pickup and ensure accurate

clocking.

Two main precautions for crystal PC board layout should be

followed:

1. Do not run the serial bus lines or any high speed logic

lines in the vicinity of the crystal. These logic level lines

can induce noise in the oscillator circuit to cause

misclocking.

2. Add a ground trace around the crystal with one end

terminated at the chip ground. This will provide

termination for emitted noise in the vicinity of the RTC

device.

In addition, it is a good idea to avoid a ground plane under

the X1 and X2 pins and the crystal, as this will affect the load

capacitance and therefore the oscillator accuracy of the

circuit. If the F

OUT

pin is used as a clock, it should be routed

away from the RTC device as well. The traces for the VBAT

and V

pins can be treated as a ground, and should be

routed around the crystal.

AC Input Circuits

The AC input ideally will have a 2.5V

P-P

sine wave at the

input, so this is the target for any signal conditioning circuitry

for the 50/60Hz waveform. Note that the peak-to-peak

amplitude can range from 1V

P-P

up to V

, although it is

best to keep the max signal level just below V

. The AC

input provides DC offset so AC coupling with a series

capacitor is advised.

If the AC power supply has a transformer, the secondary

output can be used for clocking with a resistor divider and

series AC coupling capacitor. A sample circuit is shown in

Figure 12. Values for R

are chosen depending on the

peak-to-peak range on the secondary voltage in order to

match the input of the ISL12032. C

can be sized to pass

up to 300Hz or so, and in most cases, 0.47µF should be the

selected value for a ±20% tolerance device.

The AC input to the IS12032 can be damaged if subjected to

a normal AC waveform when V

is powered down. this can

happen in circuits where there is a local LDO or power

switch for placing circuitry in standby, while the AC main is

still switched ON. Figure 11 shows a modified version of the

Figure 12 circuit, which uses an emitter follower to

essentially turn off the AC input waveform if the V

supply

goes down.

Using the ISL12032 with No AC Input

Some applications may need all the features of the

ISL12032 but do not have access to the power line AC clock,

or do not need the accuracy provided by that clock. In these

cases there is no problem using the crystal oscillator as the

primary clock source for the device.

The user must simply set the ACENB bit in register 13h to

“1”, which disables the AC input pin and forces the device to

use the crystal oscillator exclusively for the RTC and F

OUT

clock source. Setting this bit to “1” also will cause the

ACRDY bit in the SRAC register to be set to “1”, indicating

that there can be no fault with the AC input clock since it is

not used.

TABLE 28. SUGGESTED SURFACE MOUNT CRYSTALS

MANUFACTURER PART NUMBER

Citizen CM200S

Epson MC-405, MC-406

Raltron RSM-200S

SaRonix 32S12

Ecliptek ECPSM29T-32.768K

ECS ECX-306

Fox FSM-327

ISL12032

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ISL12032IVZ

Mfr. #:

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Manufacturer:

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Description:

Real Time Clock REAL TIME CLK W/ EEPROM 14LD

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ISL12032IVZ

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