7
FN6618.3
May 5, 2011
SDA vs SCL Timing
Symbol Table
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
WAVEFORM INPUTS OUTPUTS
Must be steady Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A Center Line is
High Impedance
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH V
DD
= 5.0V
SDA
AND
IRQ
/F
OUT
1533
100pF
5.0V
FOR V
OL
= 0.4V
AND I
OL
= 3mA
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V
DD
= 5V
ISL12032
8
FN6618.3
May 5, 2011
General Description
The ISL12032 device is a low power real time clock with
50/60 AC input for timing synchronization. It also has an
oscillator utilizing an external crystal for timing back-up,
clock/calendar registers, intelligent battery back-up
switching, battery voltage monitor, brownout indicator,
integrated trickle charger for super capacitor, single periodic
or polled alarms, POR supervisory function, and up to 4
Event Detect with time stamp. There are 128 bytes of
battery-backed user SRAM.
The oscillator uses a 50/60 cycle sine wave input, backed by
an external, low-cost, 32.768kHz crystal. The real time clock
tracks time with separate registers for hours, minutes, and
seconds. The calendar registers contain the date, month,
year, and day of the week. The calendar is accurate through
year 2100, with automatic leap year correction and auto
daylight savings correction.
The ISL12032’s alarm can be set to any clock/calendar
value for a match. Each alarm’s status is available by
checking the Status Register. The device also can be
configured to provide a hardware interrupt via the IRQ
pin.
There is a repeat mode for the alarms allowing a periodic
interrupt every minute, every hour, every day, etc.
The device also offers a backup power input pin. This VBAT
pin allows the device to be backed up by battery or Super
Capacitor with automatic switchover from V
DD
to VBAT. The
ISL12032 devices are specified for V
DD
= 2.7V to 5.5V and
the clock/calendar portion of the device remains fully
operational in battery backup mode down to 1.8V (Standby
Mode). The VBAT level is monitored and warnings are
reported against preselected levels. The first report is
registered when the VBAT level falls below 85% of nominal
level, the second level is set for 75% of nominal level.
Battery levels are stored in the PWRBAT registers.
The ISL12032 offers a “Brownout” alarm once the V
DD
falls
below a pre-selected trip level. In the ISL12032, this allows
the system microcontroller to save vital information to
memory before complete power loss. There are six V
DD
trip
levels for the brownout alarm.
The event detection function accepts a normally low logic
input, and when triggered will store the time/date information
for the event. The first event is stored in the memory until
reset; subsequent events are stored on-chip memory and
the last 3 events are retained and accessible by performing
an indexed register read.
Pin Descriptions
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal
is used with the device to supply a backup timebase for the
real time clock if there is no AC input. The device also can
be driven directly from a 32.768kHz source at pin X1, in
which case, pin X2 should be left unconnected. No external
load capacitors are needed for the X1 and X2 pins.
VBAT (Battery Input)
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event that the VDD
supply fails. This pin can be connected to a battery, a Super
Capacitor or tied to ground if not used.
AC (AC Input)
The AC input is the main clock input for the real time clock. It
can be either 50Hz or 60Hz, sine wave. The preferred
amplitude is 2.5V
P-P
, although amplitudes >0.25V
DD
are
acceptable. An AC coupled (series capacitor) sine wave
clock waveform is desired as the AC clock input provides DC
biasing.
LV (Low Voltage)
This pin indicates the VDD supply is below the programmed
level. This signal notifies a host processor that the main
supply is low and requests action. It is an open drain active
LOW output.
EVIN (Event Input)
The EVIN pin input detects an externally monitored event.
When a HIGH signal is present at the EVIN pin, an “event” is
detected.This input may be used for various monitoring
functions, such as the opening of a detection switch on a
chassis or door. The event detection circuit can be user
enabled or disabled (see EVIN bit) and provides the option
to be operational in battery backup modes (see EVATB bit).
When the event detection is disabled, the EVIN pin is gated
OFF. See “Functional Pin Descriptions” on page 3 for more
details.
EVDET (Event Detect Output)
The EVDET is an open drain output, which will go low when
an event is detected at the EVIN pin. If the event detection
function is enabled, the EVDET
output will go LOW and stay
there until the EVT bit is cleared.
FIGURE 2. RECOMMENDED CRYSTAL CONNECTION
X1
X2
ISL12032
9
FN6618.3
May 5, 2011
IRQ (Interrupt Output)
This pin provides an interrupt signal output. This signal
notifies a host processor that an alarm has occurred and
requests action. It is an open drain active LOW output.
F
OUT
(Frequency Output)
This pin outputs a clock signal, which is related to the crystal
frequency. The frequency output is user selectable and
enabled via the I
2
C bus. The options include seven different
frequencies or disable. It is a CMOS output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
gated). It is disabled when the backup power supply on the
VBAT pin is activated to minimize power consumption.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out
of the device. It has an open drain output and may be OR’ed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor.
The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is
designed for 400kHz I
2
C interface speeds. It is disabled
when the backup power supply on the VBAT pin is activated.
V
DD
, GND
Chip power supply and ground pins. The device will operate
with a power supply from V
DD
= 2.7V to 5.5VDC. A 0.1µF
capacitor is recommended on the V
DD
pin to ground.
Functional Description
Power Control Operation
The power control circuit accepts a V
DD
and a VBAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
the ISL12032 for up to 10 years. Another option is to use a
Super Capacitor for applications where V
DD
is interrupted
for up to a month. See the “Application Section” on page 24
for more information.
Normal Mode (V
DD
) to Battery Backup Mode
(VBAT)
To transition from the V
DD
to VBAT mode, both of the
following conditions must be met:
Condition 1:
V
DD
< VBAT - V
BATHYS
where V
BATHYS
50mV
Condition 2:
V
DD
< V
TRIP
where V
TRIP
2.2V
Battery Backup Mode (VBAT) to Normal Mode
(V
DD
)
The ISL12032 device will switch from the VBAT to V
DD
mode when one
of the following conditions occurs:
Condition 1:
V
DD
> VBAT + V
BATHYS
where V
BATHYS
50mV
Condition 2:
V
DD
> V
TRIP
+ V
TRIPHYS
where V
TRIPHYS
30mV
These power control situations are illustrated in Figures 3
and Figure 4.
The I
2
C bus is normally deactivated in battery backup mode
to reduce power consumption, but can be enabled by setting
the I
2
CBAT bit. All the other inputs and outputs of the
ISL12032 are active during battery backup mode unless
disabled via the control register.
Power Failure Detection
The ISL12032 provides a Real Time Clock Failure Bit
(RTCF) to detect total power failure. It allows users to
determine if the device has powered up after having lost all
power to the device (both V
DD
and VBAT very near
0.0VDC). Note that in cases where the VBAT input is at 0.0V
and the V
DD
input dips to <1.8V, then recovers to normal
level, the SRAM registers may not retain their values
(corrupted bits or bytes may result).
VBAT
- V
BATHYS
VBAT
VBAT
+ V
BATHYS
BATTERY BACKUP
MODE
V
DD
V
TRIP
2.2V
1.8V
FIGURE 3. BATTERY SWITCHOVER WHEN VBAT
< V
TRIP
FIGURE 4. BATTERY SWITCHOVER WHEN VBAT
> V
TRIP
V
TRIP
VBAT
V
TRIP
+ V
TRIPHYS
BATTERY BACKUP
MODE
V
DD
V
TRIP
3.0V
2.2V
ISL12032

ISL12032IVZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock REAL TIME CLK W/ EEPROM 14LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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