AD7711ARZ Datasheet AD7711ARZ, AD7711ANZ, AD7711ARZ-REEL | P13-P15

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AD7711

Figure 2 shows similar information to that outlined in Table I.

In these plots, however, the output rms noise is shown for the

full range of available cutoffs frequencies. The numbers given in

these plots are typical values at 25∞C.

CIRCUIT DESCRIPTION

The AD7711 is a sigma-delta A/D converter with on-chip digital

filtering for measuring wide dynamic range, low frequency signals

such as those in RTD applications, industrial control, or process

control applications. It contains a sigma-delta (or charge-bal-

ancing) ADC, a calibration microcontroller with on-chip static

RAM, a clock oscillator, a digital filter, and a bidirectional serial

communications port.

The part contains two analog input channels, a programmable

gain differential analog input, and a programmable gain single-

ended input. The gain range is from 1 to 128 allowing the part

to accept unipolar signals of 0 mV to 20 mV and 0 V to 2.5 V

or bipolar signals in the range ± 20 mV to ± 2.5 V when the

reference input voltage equals 2.5 V. The input signal to the

selected analog input channel is continuously sampled at a

rate determined by the frequency of the master clock, MCLK

IN, and the selected gain (see Table III). A charge-balancing

A/D converter (sigma-delta modulator) converts the sampled

signal into a digital pulse train whose duty cycle contains the

digital information. The programmable gain function on the

analog input is also incorporated in this sigma-delta modulator

with the input sampling frequency being modified to give the

higher gains. A sinc

digital low-pass filter processes the out-

put of the sigma-delta modulator and updates the output

this filter. The output data can be read from the serial port

randomly or periodically at any rate up to the output register

update rate. The first notch of this digital filter (and therefore

its –3 dB frequency) can be programmed via an on-chip con-

trol register. The programmable range for this first notch

frequency is 9.76 Hz to 1.028 kHz, giving a programmable range

for the –3 dB frequency of 2.58 Hz to 269 Hz.

The basic connection diagram for the part is shown in Figure 3.

This figure shows the AD7711 in the external clocking mode

with both the AV

and DV

pins of the AD7711 being driven

from the analog 5 V supply. Some applications have separate

supplies for both AV

and DV

, and in some cases, the ana-

log supply exceeds the 5 V digital supply (see the Power Sup-

plies and Grounding section).

ANALOG

+5V SUPPLY

10␮F 0.1␮F 0.1␮F

AIN1(+)

AIN1(–)

AIN2

RTD1

AGND

DGND

REF OUT

REF IN(+)

BIAS

REF IN(–)

RTD2

DRDY

TFS

RFS

SDATA

SCLK

MODE

SYNC

MCLK OUT

MCLK IN

AD7711

DIFFERENTIAL

ANALOG INPUT

SINGLE-ENDED

ANALOG INPUT

ANALOG GROUND

DIGITAL GROUND

DATA READY

TRANSMIT (WRITE)

RECEIVE (READ)

SERIAL DATA

SERIAL CLOCK

ADDRESS INPUT

+5V

Figure 3. Basic Connection Diagram

The AD7711 provides a number of calibration options that can

be programmed via the on-chip control register. A calibration

cycle may be initiated at any time by writing to this control

calibration microcontroller and SRAM to store calibration

parameters. Other system components may also be included in

the calibration loop to remove offset and gain errors in the input

channel using the system calibration mode. Another option is a

background calibration mode where the part continuously

performs self-calibration and updates the calibration coeffi-

cients. Once the part is in this mode, the user does not have to

issue periodic calibration commands to the device or recalibrate

when there is a change in the ambient temperature or power

supply voltage.

The AD7711 gives the user access to the on-chip calibration

registers, allowing the microprocessor to read the device calibra-

tion coefficients and also to write its own calibration coefficients

to the part from prestored values in E

PROM. This gives the

NOTCH FREQUENCY – Hz

10000

1000

0.1

10 10000100

OUTPUT NOISE – ␮V

1000

100

GAIN OF 1

GAIN OF 2

GAIN OF 4

GAIN OF 8

Figure 2a. Output Noise vs. Gain and Notch

Frequency (Gains of 1 to 8)

NOTCH FREQUENCY – Hz

1000

0.1

10 10000100

OUTPUT NOISE – ␮V

1000

100

GAIN OF 16

GAIN OF 32

GAIN OF 128

GAIN OF 64

Figure 2b. Output Noise vs. Gain and Notch

Frequency (Gains of 16 to 128)

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AD7711

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microprocessor much greater control over the AD7711’s cali-

bration procedure. It also means that the user can verify the

calibration is correct by comparing the coefficients after calibra-

tion with prestored values in E

PROM.

The AD7711 can be operated in single-supply systems provided

that the analog input voltage does not go more negative than

–30 mV. For larger bipolar signals, a V

of –5 V is required by

the part. For battery operation, the AD7711 also offers a pro-

grammable standby mode that reduces idle power consumption

to typically 7 mW.

THEORY OF OPERATION

The general block diagram of a sigma-delta ADC is shown in

Figure 4. It contains the following elements:

∑ A sample-hold amplifier.

∑ A differential amplifier or subtracter.

∑ An analog low-pass filter.

∑ A 1-bit A/D converter (comparator).

∑ A 1-bit DAC.

∑ A digital low-pass filter.

ANALOG

LOW-PASS

FILTER

DIGITAL

FILTER

DIGITAL

DATA

–

S/H AMP

DAC

COMPARATOR

Figure 4. General Sigma-Delta ADC

In operation, the analog signal sample is fed to the subtracter,

along with the output of the 1-bit DAC. The filtered difference

signal is fed to the comparator, which samples the difference

signal at a frequency many times that of the analog signal sampling

frequency (oversampling).

Oversampling is fundamental to the operation of sigma-delta

ADCs. Using the quantization noise formula for an ADC,

SNR = (6.02 ¥ number of bits + 1.76) dB,

a 1-bit ADC or comparator yields an SNR of 7.78 dB.

The AD7711 samples the input signal at a frequency of 39 kHz or

greater (see Table III). As a result, the quantization noise is

spread over a much wider frequency than that of the band of

interest. The noise in the band of interest is reduced still further

by analog filtering in the modulator loop, which shapes the

quantization noise spectrum to move most of the noise energy to

frequencies outside the bandwidth of interest. The noise perfor-

mance is thus improved from this 1-bit level to the performance

outlined in Tables I and II and in Figure 2.

The output of the comparator provides the digital input for the

1-bit DAC, so that the system functions as a negative feedback

loop that tries to minimize the difference signal. The digital data

that represents the analog input voltage is contained in the duty

cycle of the pulse train appearing at the output of the compara-

tor. It can be retrieved as a parallel binary data-word using a

digital filter.

Sigma-delta ADCs are generally described by the order of the

analog low-pass filter. A simple example of a first-order sigma-

delta ADC is shown in Figure 5. This contains only a first-order

low-pass filter or integrator. It also illustrates the derivation of

the alternative name for these devices, charge-balancing ADCs.

DAC

COMPARATOR

+FS

–FS

INTEGRATOR

DIFFERENTIAL

AMPLIFIER

兰

Figure 5. Basic Charge-Balancing ADC

The device consists of a differential amplifier (whose output is

the difference between the analog input and the output of a

1-bit DAC), an integrator, and a comparator. The term charge-

balancing comes from the fact that this system is a negative

feedback loop that tries to keep the net charge on the integrator

capacitor at zero, by balancing charge injected by the input

voltage with charge injected by the 1-bit DAC. When the analog

input is zero, the only contribution to the integrator output

comes from the 1-bit DAC. For the net charge on the integrator

capacitor to be zero, the DAC output must spend half its time at

+FS and half its time at –FS. Assuming ideal components, the

duty cycle of the comparator will be 50%.

When a positive analog input is applied, the output of the 1-bit

DAC must spend a larger proportion of the time at +FS, so the

duty cycle of the comparator increases. When a negative input

voltage is applied, the duty cycle decreases.

The AD7711 uses a second-order sigma-delta modulator and a

digital filter that provides a rolling average of the sampled out-

put. After power-up, or if there is a step change in the input

voltage, there is a settling time that must elapse before valid

data is obtained.

Input Sample Rate

The modulator sample frequency for the device remains at

CLK IN

/512 (19.5 kHz @ f

CLK IN

= 10 MHz) regardless of the

selected gain. However, gains greater than ¥1 are achieved by a

combination of multiple input samples per modulator cycle and

scaling the ratio of reference capacitor to input capacitor. As a

result of the multiple sampling, the input sample rate of

the device varies with the selected gain (see Table III). The

effective input impedance is 1/C ¥ f

where C is the input sam-

pling capacitance and f

is the input sample rate.

Table III. Input Sampling Frequency vs. Gain

Gain Input Sampling Frequency (f

)

CLK IN

/256 (39 kHz @ f

CLK IN

= 10 MHz)

22 ¥ f

CLK IN

/256 (78 kHz @ f

CLK IN

= 10 MHz)

44 ¥ f

CLK IN

/256 (156 kHz @ f

CLK IN

= 10 MHz)

88 ¥ f

CLK IN

/256 (312 kHz @ f

CLK IN

= 10 MHz)

16 8 ¥ f

CLK IN

/256 (312 kHz @ f

CLK IN

= 10 MHz)

32 8 ¥ f

CLK IN

/256 (312 kHz @ f

CLK IN

= 10 MHz)

64 8 ¥ f

CLK IN

/256 (312 kHz @ f

CLK IN

= 10 MHz)

128 8 ¥ f

CLK IN

/256 (312 kHz @ f

CLK IN

= 10 MHz)

DIGITAL FILTERING

The AD7711’s digital filter behaves like a similar analog filter,

with a few minor differences.

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AD7711

First, since digital filtering occurs after the A-to-D conversion

process, it can remove noise injected during the conversion

process. Analog filtering cannot do this.

On the other hand, analog filtering can remove noise super-

imposed on the analog signal before it reaches the ADC. Digital

filtering cannot do this, and noise peaks riding on signals near

full scale have the potential to saturate the analog modulator

and digital filter, even though the average value of the signal is

within limits. To alleviate this problem, the AD7711 has

overrange headroom built into the sigma-delta modulator and

digital filter, which allows overrange excursions of 5% above the

analog input range. If noise signals are larger than this, consid-

eration should be given to analog input filtering, or to reducing

the input channel voltage so that its full scale is half that of the

analog input channel full scale. This will provide an overrange

capability greater than 100% at the expense of reducing the

dynamic range by 1 bit (50%).

Filter Characteristics

The cutoff frequency of the digital filter is determined by the

value loaded to Bits FS0 to FS11 in the control register. At the

maximum clock frequency of 10 MHz, the minimum cutoff

frequency of the filter is 2.58 Hz while the maximum program-

mable cutoff frequency is 269 Hz.

Figure 6 shows the filter frequency response for a cutoff fre-

quency of 2.62 Hz, which corresponds to a first filter notch fre-

quency of 10 Hz. This is a (sinx/x)

response (also called sinc

)

that provides >100 dB of 50 Hz and 60 Hz rejection. Program-

ming a different cutoff frequency via FS0–FS11 does not alter

the profile of the filter response; it changes the frequency of the

notches as outlined in the Control Register section.

FREQUENCY – Hz

–200

GAIN – dB

–20

–80

–140

–160

–180

–40

–60

–100

–120

–220

–240

6010 20 30 40 50

Figure 6. Frequency Response of AD7711 Filter

Since the AD7711 contains this on-chip, low-pass filtering,

there is a settling time associated with step function inputs, and

data on the output will be invalid after a step change until the

settling time has elapsed. The settling time depends upon the

notch frequency chosen for the filter. The output data rate

equates to this filter notch frequency and the settling time of the

filter to a full-scale step input is four times the output data

period. In applications using both input channels, the settling

time of the filter must be allowed to elapse before data from

the second channel is accessed.

Post Filtering

The on-chip modulator provides samples at a 19.5 kHz output

rate. The on-chip digital filter decimates these samples to provide

data at an output rate that corresponds to the programmed first

notch frequency of the filter. Since the output data rate ex-

ceeds the Nyquist criterion, the output rate for a given band-

width will satisfy most application requirements. However,

there may be some applications that require a higher data rate

for a given bandwidth and noise performance. Applications

that need this higher data rate will require some post filtering

following the digital filter of the AD7711.

For example, if the required bandwidth is 7.86 Hz but the required

update rate is 100 Hz, the data can be taken from the AD7711

at the 100 Hz rate giving a –3 dB bandwidth of 26.2 Hz. Post

filtering can be applied to this to reduce the bandwidth and

output noise to the 7.86 Hz bandwidth level, while maintaining

an output rate of 100 Hz.

Post filtering can also be used to reduce the output noise from

the device for bandwidths below 2.62 Hz. At a gain of 128, the

output rms noise is 250 nV. This is essentially device noise or

white noise, and since the input is chopped, the noise has a flat

frequency response. By reducing the bandwidth below 2.62 Hz,

the noise in the resultant pass band can be reduced. A reduction

in bandwidth by a factor of 2 results in a ÷2 reduction in the

output rms noise. This additional filtering will result in a longer

settling time.

Antialias Considerations

The digital filter does not provide any rejection at integer mul-

tiples of the modulator sample frequency (n ¥ 19.5 kHz, where

n = 1, 2, 3 . . . ). This means that there are frequency bands,

± f

3 dB

wide (f

3 dB

is the cutoff frequency selected by FS0 to FS11),

where noise passes unattenuated to the output. However, due to

the AD7711’s high oversampling ratio, these bands occupy only

a small fraction of the spectrum, and most broadband noise is

filtered. In any case, because of the high oversampling ratio a

simple, RC, single-pole filter is generally sufficient to attenuate

the signals in these bands on the analog input and thus provide

adequate antialiasing filtering.

If passive components are placed in front of the AD7711, care

must be taken to ensure that the source impedance is low enough

so as not to introduce gain errors in the system. The dc input

impedance for the AD7711 is over 1 GW. The input appears as

a dynamic load that varies with the clock frequency and with the

selected gain (see Figure 7). The input sample rate, as shown

in Table III, determines the time allowed for the analog input

capacitor, C

, to be charged. External impedances result in a

longer charge time for this capacitor, which may result in gain

errors being introduced on the analog inputs. Table IV shows the

allowable external resistance/capacitance values such that no

gain error to the 16-bit level is introduced while Table V shows

the allowable external resistance/capacitance values such that no

gain error to the 20-bit level is introduced. Both inputs of the

differential input channel (AIN1) look into similar input circuitry.

HIGH

IMPEDANCE

>1G⍀

INT

11.5pF TYP

BIAS

INT

7k⍀ TYP

AIN

SWITCHING FREQUENCY DEPENDS

CLKIN

AND SELECTED GAIN

AD7711

Figure 7. Analog Input Impedance

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Analog to Digital Converters - ADC CMOS 24B w/ Matched RTD Excitation Crnt

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