AD7711ARZ Datasheet AD7711ARZ, AD7711ANZ, AD7711ARZ-REEL | P25-P27

REV. G

–24–

AD7711

SIMPLIFYING THE EXTERNAL CLOCKING MODE

INTERFACE

In many applications, the user may not need to write to the

on-chip calibration registers. In this case, the serial interface to

the AD7711 in external clocking mode can be simplified by

connecting the TFS line to the A0 input of the AD7711 (see

Figure 14). This means that any write to the device will load

data to the control register (because A0 is low while TFS is

low), and any read to the device will access data from the output

data register or from the calibration registers (because A0 is high

while RFS is low). Note that in this arrangement, the user does

not have the capability of reading from the control register.

AD7711

RFS

SDATA

SCLK

TFS

FOUR

INTERFACE

LINES

Figure 14. Simplified Interface with

TFS

Connected to A0

Another method of simplifying the interface is to generate the

TFS signal from an inverted RFS signal. However, generating

the signals the opposite way around (RFS from an inverted

TFS) will cause writing errors.

MICROCOMPUTER/MICROPROCESSOR INTERFACING

The AD7711’s flexible serial interface allows easy interface to

most microcomputers and microprocessors. Figure 15 shows a

flowchart for a typical programming sequence for reading data

from the AD7711 to a microcomputer, while Figure 16 shows a

flowchart for writing data to the AD7711. Figures 17, 18, and

19 show some typical interface circuits.

Figure 15 shows continuous read operations from the AD7711

output register where the DRDY line is continuously polled.

Depending on the microprocessor configuration, the DRDY line

may come to an interrupt input, in which case DRDY will auto-

matically generate an interrupt without being polled. The read-

ing of the serial buffer could be anything from one read

operation up to three read operations (where 24 bits of data

are read into an 8-bit serial register). A read operation to the

control/calibration registers is similar, but, in this case, the status

of DRDY can be ignored. The A0 line is brought low when the

RFS line is brought low during a read from the control register.

The flowchart also shows the bits being reversed after they have

been read in from the serial port. This depends on whether the

microprocessor expects the MSB of the word first or the LSB of

the word first. The AD7711 outputs the MSB first.

YES

BRING

RFS LOW

ⴛ3

REVERSE

ORDER OF BITS

BRING

RFS HIGH

POLL DRDY

CONFIGURE AND

INITIALIZE ␮C/␮P

SERIAL PORT

DRDY

LOW?

BRING

RFS, TFS HIGH

START

READ

SERIAL BUFFER

Figure 15. Flowchart for Continuous Read Operations

to the AD7711

Figure 16 shows a single 24-bit write operation to the AD7711

control or calibration registers. This shows data being transferred

from data memory to the accumulator before being written to

the serial buffer. Some microprocessor systems allow data to be

written directly to the serial buffer from data memory. Writing

data to the serial buffer from the accumulator generally consists

of either two or three write operations, depending on the size of

the serial buffer.

Figure 16 also shows the option of the bits being reversed before

being written to the serial buffer, which depends on whether the

first bit transmitted by the microprocessor is the MSB or the

LSB. The AD7711 expects the MSB as the first bit in the data

stream. In cases where the data is being read or being written in

bytes and the data has to be reversed, the bits have to be reversed

for every byte.

REV.G

AD7711

–25–

START

WRITE DATA FROM

ACCUMULATOR TO

SERIAL BUFFER

BRING

TFS AND A0 LOW

LOAD DATA FROM

ADDRESS TO

ACCUMULATOR

CONFIGURE AND

INITIALIZE ␮C/␮P

SERIAL PORT

BRING

RFS, TFS AND

A0 HIGH

BRING

TFS AND A0 HIGH

END

ⴛ3

REVERSE

ORDER OF

BITS

Figure 16. Flowchart for Single Write Operation

to the AD7711

AD7711 to 8051 Interface

Figure 17 shows an interface between the AD7711 and the 8XC51

microcontroller. The AD7711 is configured for external clocking

mode, while the 8XC51 is configured in its Mode 0 serial interface

mode. The DRDY line from the AD7711 is connected to the Port

P1.2 input of the 8XC51, so the DRDY line is polled by the

8XC51. The DRDY line can be connected to the INT1 input of

the 8XC51 if an interrupt driven system is preferred.

P1.0

P3.0

P3.1

P1.1

P1.2

P1.3

8XC51

AD7711

SDATA

RFS

TFS

MODE

DRDY

SYNC

SCLK

Figure 17. AD7711 to 8XC51 Interface

Table VII shows some typical 8XC51 code used for a single 24-bit

read from the output register of the AD7711. Table VIII shows

some typical code for a single write operation to the control

write operation, while the AD7711 expects the MSB first so the

data to be transmitted has to be rearranged before being written

to the output serial register. Similarly, the AD7711 outputs the

MSB first during a read operation that the 8XC51 expects the

LSB first. Therefore, the data that is read into the serial buffer

needs to be rearranged before the correct data-word from the

AD7711 is available in the accumulator.

Table VII. 8XC51 Code for Reading from the AD7711

MOV SCON,#00010001B; Configure 8051 for MODE 0

MOV IE,#00010000B; Disable All Interrupts

SETB 90H; Set P1.0, Used as RFS

SETB 91H; Set P1.1, Used as TFS

SETB 93H; Set P1.3, Used as A0

MOV R1,#003H; Sets Number of Bytes to Be Read in

Read Operation

MOV R0,#030H; Start Address for where Bytes Will

Be Loaded

MOV R6,#004H; Use P1.2 as DRDY

WAIT:

NOP;

MOV A,P1; Read Port 1

ANL A,R6; Mask Out All Bits Except DRDY

JZ READ; If Zero Read

SJMP WAIT; Otherwise Keep Polling

READ:

CLR 90H; Bring RFS Low

CLR 98H; Clear Receive Flag

POLL:

JB 98H, READ1 Tests Receive Interrupt Flag

SJMP POLL

READ 1:

MOV A,SBUF; Read Buffer

RLC A; Rearrange Data

MOV B.0,C; Reverse Order of Bits

RLC A; MOV B.1,C; RLC A; MOV B.2,C;

RLC A; MOV B.3,C; RLC A; MOV B.4,C;

RLC A; MOV B.5,C; RLC A; MOV B.6,C;

RLC A; MOV B.7,C;

MOV A,B;

MOV @R0,A; Write Data to Memory

INC R0; Increment Memory Location

DEC R1 Decrement Byte Counter

MOV A,R1

JZ END Jump if Zero

JMP WAIT Fetch Next Byte

END:

SETB 90H Bring RFS High

FIN:

SJMP FIN

REV. G

–26–

AD7711

Table VIII. 8XC51 Code for Writing to the AD7711

MOV SCON,#00000000B; Configure 8051 for MODE 0

and Enable Serial Reception

MOV IE,#10010000B; Enable Transmit Interrupt

MOV IP,#00010000B; Prioritize the Transmit Interrupt

SETB 91H; Bring TFS High

SETB 90H; Bring RFS High

MOV R1,#003H; Sets Number of Bytes to Be Written

in a Write Operation

MOV R0,#030H; Start Address in RAM for Bytes

MOV A,#00H; Clear Accumulator

MOV SBUF,A; Initialize the Serial Port

WAIT:

JMP WAIT; Wait for Interrupt

INT ROUTINE:

NOP; Interrupt Subroutine

MOV A,R1; Load R1 to Accumulator

JZ FIN; If Zero Jump to FIN

DEC R1; Decrement R1 Byte Counter

MOV A,@R; Move Byte into the Accumulator

INC R0; Increment Address

RLC A; Rearrange Data from LSB First

to MSB First

MOV B.0,C; RLC A; MOV B.1,C; RLC A;

MOV B.2,C; RLC A; MOV B.3,C; RLC A;

MOV B.4,C; RLC A; MOV B.5,C; RLC A;

MOV B.6,C; RLC A; MOV B.7,C; MOV A,B;

CLR 93H; Bring A0 Low

CLR 91H; Bring TFS Low

MOV SBUF,A; Write to Serial Port

RETI; Return from Subroutine

FIN:

SETB 91H; Set TFS High

SETB 93H; Set A0 High

RETI; Return from Interrupt Subroutine

AD7711 to 68HC11 Interface

Figure 18 shows an interface between the AD7711 and the

68HC11 microcontroller. The AD7711 is configured for its

external clocking mode, while the SPI port is used on the

68HC11 is in single-chip mode. The DRDY line from the

AD7711 is connected to the Port PC2 input of the 68HC11, so

the DRDY line is polled by the 68HC11. The DRDY line can

be connected to the IRQ input of the 68HC11 if an interrupt

driven system is preferred. The 68HC11 MOSI and MISO lines

should be configured for wire-OR operation. Depending on the

interface configuration, it may be necessary to provide bidirec-

tional buffers between the 68HC11 MOSI and MISO lines.

The 68HC11 is configured in the master mode with its CPOL

Logic 0 bit set to a Logic 0 and its CPHA bit set to a Logic 1.

With a 10 MHz master clock on the AD7711, the interface will

operate with all four serial clock rates of the 68HC11.

AD7711

SDATA

SCLK

RFS

TFS

PC0

MISO

SCK

PC1

PC2

MODE

PC3

DRDY

SYNC

68HC11

MOSI

Figure 18. AD7711 to 68HC11 Interface

APPLICATIONS

4-Wire RTD Configurations

Figure 19 shows a 4-wire RTD application where the RTD

transducer is interfaced directly to the AD7711. In the 4-wire

configuration, there are no errors associated with lead resistances

because no current flows in the measurement leads connected to

AIN1(+) and AIN1(–). One of the RTD current sources is used

to provide the excitation current for the RTD. A common nominal

resistance value for the RTD is 100 W and, therefore, the RTD

will generate a 20 mV signal that can be handled directly by the

analog input of the AD7711. In the circuit shown, the second

RTD excitation current is used to generate the reference voltage

for the AD7711. This reference voltage is developed across R

REF

and applied to the differential reference inputs. For the nominal

reference voltage of 2.5 V, R

REF

is 12.5 kW. This scheme ensures

that the analog input voltage span remains ratiometric to the

reference voltage. Any errors in the analog input voltage due to

the temperature drift of the RTD current source is compensated

for by the variation in the reference voltage. The typical matching

between the RTD current sources is less than 3 ppm/∞C.

INTERNAL

CIRCUITRY

200␮A

PGA

AD7711

A = 1–128

RTD2

REF IN(+)

REF IN(–)

RTD1

AIN1(+)

AIN1(–)

AGND

REF

RTD

DGND

Figure 19. 4-Wire RTD Application with the AD7711

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD7711ARZ

Mfr. #:

Buy AD7711ARZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC CMOS 24B w/ Matched RTD Excitation Crnt

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AD7711ARZ

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