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AD7711ARZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
Parameter A, S Versions
1
Unit Conditions/Comments
V
BIAS
INPUT
12
Input Voltage Range AV
DD
– 0.85 ¥ V
REF
See V
BIAS
Input Section
or AV
DD
– 3.5 V max Whichever Is Smaller; +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
or AV
DD
– 2.1 V max Whichever Is Smaller; +5 V/0 V Nominal AV
DD
/V
SS
V
SS
+ 0.85 ¥ V
REF
See V
BIAS
Input Section
or V
SS
+ 3 V min Whichever Is Greater; +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
or V
SS
+ 2.1 V min Whichever Is Greater; +5 V/0 V Nominal AV
DD
/V
SS
V
BIAS
Rejection 65 to 85 dB typ Increasing with Gain
LOGIC INPUTS
Input Current ± 10 mA max
All Inputs except MCLK IN
V
INL
, Input Low Voltage 0.8 V max
V
INH
, Input High Voltage 2.0 V min
MCLK IN Only
V
INL
, Input Low Voltage 0.8 V max
V
INH
, Input High Voltage 3.5 V min
LOGIC OUTPUTS
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 1.6 mA
V
OH
, Output High Voltage 4.0 V min I
SOURCE
= 100 mA
Floating State Leakage Current ± 10 mA max
Floating State Output Capacitance
13
9 pF typ
TRANSDUCER BURNOUT
Current 4.5 mA nom
Initial Tolerance @ 25∞C ± 10 % typ
Drift 0.1 %/∞C typ
RTD EXCITATION CURRENTS (RTD1, RTD2)
Output Current 200 mA nom
Initial Tolerance @ 25∞C ± 20 % max
Drift 20 ppm/∞C typ
Initial Matching @ 25∞C ± 1% max Matching between RTD1 and RTD2 Currents
Drift Matching 3 ppm/∞C typ Matching between RTD1 and RTD2 Current Drift
Line Regulation (AV
DD
) 200 nA/V max AV
DD
= 5 V
Load Regulation 200 nA/V max
Output Compliance AV
DD
– 2 V max
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
14
(1.05 ¥ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (between 1 and 128)
Negative Full-Scale Calibration Limit
14
–(1.05 ¥ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (between 1 and 128)
Offset Calibration Limit
15
–(1.05 ¥ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (between 1 and 128)
Input Span
15
0.8 ¥ V
REF
/GAIN V min GAIN Is the Selected PGA Gain (between 1 and 128)
(2.1 ¥ V
REF
)/GAIN V max GAIN Is the Selected PGA Gain (between 1 and 128)
NOTES
12
The AD7711 is tested with the following V
BIAS
voltages. With AV
DD
= 5 V and V
SS
= 0 V, V
BIAS
= 2.5 V; with AV
DD
= 10 V and V
SS
= 0 V, V
BIAS
= 5 V, and
with AV
DD
= 5 V and V
SS
= –5 V, V
BIAS
= 0 V.
13
Guaranteed by design, not production tested.
14
After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, the device outputs all 0s.
15
These calibration and span limits apply, provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
–3–REV. G
AD7711
ORDERING GUIDE
Model Temperature Range Package Option*
AD7711AN –40∞C to +85∞C N-24
AD7711AR –40∞C to +85∞C R-24
AD7711AR-REEL –40∞C to +85∞C R-24
AD7711AR-REEL7 –40∞C to +85∞C R-24
AD7711AQ –40∞C to +85∞CQ-24
AD7711SQ –55∞C to +125∞CQ-24
EVAL-AD7711EB Evaluation Board
*N = Plastic DIP, Q = CERDIP, R = SOIC.
Parameter A, S Versions
1
Unit Conditions/Comments
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage
16
5 to 10 V nom ± 5% for Specified Performance
DV
DD
Voltage
17
5V nom ± 5% for Specified Performance
AV
DD
– V
SS
Voltage 10.5 V max For Specified Performance
Power Supply Currents
AV
DD
Current 4 mA max
DV
DD
Current 4.5 mA max
V
SS
Current 1.5 mA max V
SS
= –5 V
Power Supply Rejection
18
Rejection w.r.t. AGND; Assumes V
BIAS
Is Fixed
Positive Supply (AV
DD
and DV
DD
) See Note 19 dB typ
Negative Supply (V
SS
)90 dB typ
Power Dissipation
Normal Mode 45 mW max AV
DD
= DV
DD
= +5 V, V
SS
= 0 V; Typically 25 mW
52.5 mW max AV
DD
= DV
DD
= +5 V, V
SS
= –5 V; Typically 30 mW
Standby (Power-Down) Dissipation 15 mW max AV
DD
= DV
DD
= +5 V, V
SS
= 0 V or –5 V; Typically 7 mW
NOTES
16
The AD7711 is specified with a 10 MHz clock for AV
DD
voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V. Operating with AV
DD
voltages in the range 5.25 V to 10.5 V is only guaranteed over the 0∞C to 70∞C temperature range.
17
The ± 5% tolerance on the DV
DD
input is allowed provided DV
DD
does not exceed AV
DD
by more than 0.3 V.
18
Measured at dc and applies in the selected pass band. PSRR at 50 Hz will exceed 120 dB with filter notches of 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz will exceed
120 dB with filter notches of 10 Hz, 30 Hz, or 60 Hz.
19
PSRR depends on gain: Gain of 1 = 70 dB typ; Gain of 2: 75 dB typ; Gain of 4 = 80 dB typ; Gains of 8 to 128 = 85 dB typ. These numbers can be improved (to
95 dB typ) by deriving the V
BIAS
voltage (via Zener diode or reference) from the AV
DD
supply.
Specifications subject to change without notice.
AD7711–SPECIFICATIONS
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V to AV
DD
Digital Input Voltage to DGND . . . . . –0.3 V to AV
DD
+ 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DV
DD
+ 0.3 V
Operating Temperature Range
Commercial (A Version) . . . . . . . . . . . . . . . . –40∞C to +85∞C
Extended (S Version) . . . . . . . . . . . . . . . . . –55∞C to +125∞C
Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300∞C
Power Dissipation (Any Package) to 75∞C . . . . . . . . . . 450 mW
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25∞C, unless otherwise noted.)
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
AV
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
AV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +12 V
DV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
V
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
V
SS
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V
Analog Input Voltage to AGND
. . . . . . . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V to AV
DD
+ 0.3 V
Reference Input Voltage to AGND
. . . . . . . . . . . . . . . . . . . . . . . . . V
SS
– 0.3 V to AV
DD
+ 0.3 V
REV. G
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7711 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
2
REV.G
AD7711
–5–
TIMING CHARACTERISTICS
1, 2
Limit at T
MIN
, T
MAX
Parameter (A, S Versions) Unit Conditions/Comments
f
CLK IN
4, 5
400 kHz min Master Clock Frequency: Crystal Oscillator or Externally
Supplied for Specified Performance
10 MHz max
t
CLK IN LO
0.4 × t
CLK IN
ns min Master Clock Input Low Time; t
CLK IN
= 1/f
CLK IN
t
CLK IN HI
0.4 × t
CLK IN
ns min Master Clock Input High Time
t
r
6
50 ns max Digital Output Rise Time. Typically 20 ns
t
f
6
50 ns max Digital Output Fall Time. Typically 20 ns
t
1
1000 ns min SYNC Pulse Width
Self-Clocking Mode
t
2
0 ns min DRDY to RFS Setup Time
t
3
0 ns min DRDY to RFS Hold Time
t
4
2 × t
CLK IN
ns min A0 to RFS Setup Time
t
5
0 ns min A0 to RFS Hold Time
t
6
4 × t
CLK IN
+ 20 ns max RFS Low to SCLK Falling Edge
t
7
7
4 × t
CLK IN
+ 20 ns max Data Access Time (RFS Low to Data Valid)
t
8
7
t
CLK IN
/2 ns min SCLK Falling Edge to Data Valid Delay
t
CLK IN
/2
+ 30 ns max
t
9
t
CLK IN
/2 ns nom SCLK High Pulse Width
t
10
3 × t
CLK IN
/2 ns nom SCLK Low Pulse Width
t
14
50 ns min A0 to TFS Setup Time
t
15
0 ns min A0 to TFS Hold Time
t
16
4 × t
CLK IN
+ 20 ns max TFS to SCLK Falling Edge Delay Time
t
17
4 × t
CLK IN
ns min TFS to SCLK Falling Edge Hold Time
t
18
0 ns min Data Valid to SCLK Setup Time
t
19
10 ns min Data Valid to SCLK Hold Time
NOTES
1
Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figures 10 to 13.
3
The AD7711 is specified with a 10 MHz clock for AV
DD
voltages of 5 V ± 5%. It is specified with an 8 MHz clock for AV
DD
voltages greater than 5.25 V and less
than 10.5 V.
4
CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711 is not in STANDBY mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
5
The AD7711 is production tested with f
CLK IN
at 10 MHz (8 MHz for AV
DD
> 5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6
Specified using 10% and 90% points on waveform of interest.
7
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
(DV
DD
= +5 V ⴞ 5%; AV
DD
= +5 V or +10 V
3
ⴞ 5%; V
SS
= 0 V or –5 V ⴞ 10%; AGND = DGND =
0 V; f
CLK IN
= 10 MHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
, unless otherwise noted.)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

AD7711ARZ

Mfr. #:
Buy AD7711ARZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 24B w/ Matched RTD Excitation Crnt
Lifecycle:
New from this manufacturer.
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