LT3976
20
3976f
For more information www.linear.com/3976
negative resistance load to the source and can cause the
source to current limit or latch low under low source voltage
conditions. UVLO prevents the regulator from operating
at source voltages where the problems might occur. The
UVLO threshold can be adjusted by setting the values R3
and R4 such that they satisfy the following equation:
V
UVLO
= V
EN(THRESH)
R3+R4
R4
⎛
⎝
⎜
⎞
⎠
⎟
where V
EN(THRESH)
is the falling threshold of the EN pin,
which is approximately 1.02V, and where switching should
stop when V
IN
falls below V
UVLO
. Note that due to the
comparator’s hysteresis, switching will not start until the
input is about 6% above V
UVLO
.
When operating in Burst Mode operation for light load
currents, the current through the UVLO resistor network
can easily be greater than the supply current consumed
by the LT3976. Therefore, the UVLO resistors should be
large to minimize their effect on efficiency at low loads.
Soft-Start
The SS pin can be used to soft start the LT3976 by throt-
tling the maximum input current during start-up and reset.
An internal 1.8μA current source charges an external
capacitor generating a voltage ramp on the SS pin. The
SS pin clamps the internal V
C
node, which slowly ramps
up the current limit. Maximum current limit is reached
when the SS pin is about 1.5V or higher. By selecting a
large enough capacitor, the output can reach regulation
without overshoot. Figure 7 shows start-up waveforms
for a typical application with a 10nF capacitor on SS for
a 1.65Ω load when the EN
pin is pulsed high for 7ms.
The external SS capacitor is actively discharged when the
EN pin is low, or during thermal shutdown. The active
pull-down on the SS pin has a resistance of about 150Ω.
applicaTions inForMaTion
SHDN
1.02V
EN
LT3976
V
IN
R3
R4
+
–
Figure 6. Undervoltage Lockout
Figure 7. Soft-Start Waveforms for the Front-Page Application
with a 10nF Capacitor on SS. EN Is Pulsed High for About 7ms
with a 1.65Ω Load Resistor
V
OUT
1V/DIV
V
SS
0.5V/DIV
I
L
1A/DIV
1ms/DIV
3976 F07
Synchronization
To select low ripple Burst Mode operation, tie the SYNC
pin below 0.5V (this can be ground or a logic output).
Synchronizing the LT3976 oscillator to an external fre-
quency can be done by connecting a square wave (with
20% to 80% duty cycle) to the SYNC pin. The square
wave amplitude should have valleys that are below 0.5V
and peaks above 1.5V (up to 6V).
The LT3976 will pulse skip at low output loads while syn-
chronized to an external clock to maintain regulation. At
very light loads, the part will go to sleep between groups of
pulses, so the quiescent current of the part will still be low,
but not as low as in Burst Mode operation. The quiescent
current in a typical application when synchronized with an
external clock is 11µA at no load. Holding the SYNC pin
DC high yields no advantages in terms of output ripple or
minimum load to full frequency, so is not recommended.
Never float the SYNC pin.
The LT3976 may be synchronized over a 250kHz to 2MHz
range. The R
T
resistor should be chosen to set the LT3976
switching frequency 20% below the lowest synchronization
input. For example, if the synchronization
signal will be
250kHz
and higher, the R
T
should be selected for 200kHz.
To assure reliable and safe operation the LT3976 will only
synchronize when the output voltage is near regulation
as indicated by the PG flag. It is therefore necessary to
choose a large enough inductor value to supply the required
output current at the frequency set by the R
T
resistor (see
Inductor Selection section). The slope compensation is set
by the R
T
value, while the minimum slope compensation
required to avoid subharmonic oscillations is established
