LT3976
9
3976f
For more information www.linear.com/3976
pin FuncTions
FB (Pin 1/Pins 23, 24): The LT3976 regulates the FB pin
to 1.197V. Connect the feedback resistor divider tap to this
pin. Also, connect a phase lead capacitor between FB and
the output. Typically, this capacitor is 10pF.
SS (Pin 2/Pin 1): A capacitor is tied between SS and ground
to slowly ramp up the peak current limit of the LT3976 on
start-up. There is an internal 1.8μA pull-up on this pin.
The soft-start capacitor is actively discharged when the
EN pin goes low, during undervoltage lockout or thermal
shutdown. Float this pin to disable soft-start.
OUT (Pin 3/Pin 2): This pin is an input to the dropout
comparator which maintains a minimum dropout of
500mV between V
IN
and OUT. The OUT pin connects to
the anode of the internal boost diode. This pin also sup-
plies the current to the LT3976’s internal regulator when
OUT is above 3.2V. Connect this pin to the output when
the programmed output voltage is less than 16V.
BOOST (Pin 4/Pin 4): This pin is used to provide a drive
voltage, higher than the input voltage, to the internal bipolar
NPN power switch.
SW (Pins 5, 6, 7/Pins 6, 7, 8): The
SW pin is the output of
an
internal power switch. Connect these pins to the induc-
tor, catch diode, and boost capacitor. An R-C snubber to
GND is needed to ensure robustness under all conditions.
Typical values are 2Ω and 470pF.
NC (Pins 8, 9/Pins 3, 5, 9-12, 17, 22): No Connects.
These pins are not connected to internal circuitry.
V
IN
(Pins 10, 11, 12/Pins 13, 14, 15): The V
IN
pin sup-
plies current to the LT3976’s internal circuitry and to the
internal power switch. These pins must be locally bypassed.
EN (Pin 13/Pin 16): The part is in shutdown when this
pin is low and active when this pin is high. The hysteretic
threshold voltage is 1.08V going up and 1.02V going down.
The EN threshold is only accurate when V
IN
is above 4.3V.
If V
IN
is lower than 3.9V, internal UVLO will place the part
in shutdown. Tie to V
IN
if shutdown feature is not used.
RT (Pin 14/Pin 18): A resistor is tied between RT and
ground to set the switching frequency.
PG (Pin 15/Pin 19): The PG pin is the open-drain output of
an internal comparator. PGOOD remains low until the FB
pin is within 8.4% of the final regulation voltage. PGOOD
is
valid when V
IN
is above 2V.
SYNC (Pin 16/Pin 20): This is the external clock synchro-
nization input. Ground this pin for low ripple Burst Mode
operation at low output loads. Tie to a clock source for
synchronization, which will include pulse skipping at low
output loads. When in pulse-skipping mode, quiescent
current increases to 11µA in a typical application at no
load. Do not float this pin.
GND (Exposed Pad Pin 17/Pin 21, Exposed Pad Pin 25):
Ground. The exposed pad must be soldered to the PCB.
(MSE/UDD)
