LT3976
23
3976f
For more information www.linear.com/3976
Fault Tolerance of QFN Package
The QFN package is designed to tolerate single fault condi-
tions. Shorting two adjacent pins together or leaving one
single pin floating does not raise the output voltage or cause
damage to the LT3976 regulator. However, the application
circuit must meet a few requirements discussed in this
section in order to achieve this fault tolerance.
Tables 5 and 6 show the effects that result from shorting
adjacent pins or from a floating pin, respectively.
There are three items which require consideration in terms
of the application circuit to achieve fault tolerance: SS-
OUT pin short, RT-PG pin short, and PG-SYNC pin short.
FB PIN VOLTAGE (V)
0
700
600
500
400
300
200
100
0
0.6 1
3976 G22
0.2 0.4
0.8 1.2
SWITCHING FREQUENCY (kHz)
applicaTions inForMaTion
If the output voltage is less than 6V, then the application
circuit can be setup normally (see Figure 12a) because a
SS to OUT short will not violate the SS pin 6V absolute
maximum and a PG short to either RT or SYNC will not
violate the 6V absolute maximum on each of those pins.
If the output voltage is greater than 6V, the best way to
solve the problem of violating the SS absolute maximum
when shorted to OUT is to tie the OUT pin to GND. Note
that grounding the OUT pin will compromise the dropout
performance of the LT3976. When OUT is grounded, an
external Schottky diode to either the output, V
IN
, or an-
other voltage source must be used to charge the boost
capacitor. The PG pull-up resistor must be increased
Table 5. Effects of Pin Shorts
PINS EFFECT
SS-OUT V
OUT
may fall below regulation voltage for V
OUT
less than or equal to 6V. For outputs above 6V, the absolute maximum of the SS pin
would be violated, so the OUT pin must be tied to GND (see discussion in the Fault Tolerance section)
V
IN
-EN No effect. In most applications, EN is tied to V
IN
. If EN is driven with a logic signal, the customer must ensure that the circuit generating
that signal can withstand the maximum V
IN
RT-PG No effect if PG is floated. V
OUT
will fall below regulation if PG is connected to the output with a resistor pull-up as long as the resister
divider formed by the PG pin pull-up and the RT resistor prevents the RT pin absolute maximum from being violated (see discussion in
the Fault Tolerance section). In both cases, the switching frequency will be significantly increased if the output goes below regulation,
which may cause the LT3976 to go into pulse-skipping mode if the minimum on-time is violated.
PG-SYNC No effect if PG is floated. No effect if PG is connected to the output with a resistor pull-up as long as there is a resistor to GND on the
SYNC pin or the SYNC pin is tied to GND. This is to ensure that the resistor divider formed by the PG pin pull-up and the SYNC pin
resistor to GND prevents the SYNC pin Absolute Maximum from being violated (see discussion in the Fault T
olerance section).
Table 6. Effects of Floating Pins
PIN EFFECT
SS No effect; soft-start feature will not function.
OUT V
OUT
may fall below regulation voltage. With the OUT pin disconnected, the boost capacitor cannot be charged and thus the power
switch cannot fully saturate, which increases power dissipation.
BOOST V
OUT
may fall below regulation voltage. With the BOOST pin disconnected, the boost capacitor cannot be charged and thus the power
switch cannot fully saturate, which increases power dissipation.
SW No effect; there are several SW pins.
V
IN
No effect; there are several V
IN
pins.
EN V
OUT
may fall below regulation voltage. Part may work normally or be shutdown depending on how the application circuit couples to the
floating EN pin.
RT V
OUT
may fall below regulation voltage.
PG No effect.
SYNC No effect. The LT3976 may be in Burst Mode operation or pulse-skipping mode depending on how the application circuit couples to the
floating SYNC pin.
FB No effect; there are two FB pins.
GND No effect; there are several GND connections. If Exposed Pad is floated, thermal performance will be degraded.
