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ADUCM310BBCZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
Data Sheet ADuCM310
Rev. A Page 9 of 27
Parameter Min Typ Max Unit Test Conditions/Comments
Gain Error Drift Excluding internal reference drift
VDAC0, VDAC1, VDAC4, and
VDAC5
5 ppm/°C
VDAC2, VDAC3, VDAC6, and
VDAC7
10 ppm/°C
Output Impedance
VDAC0, VDAC1, VDAC4,
VDAC5, VDAC6, and VDAC7
1 Ω
VDAC2 and VDAC3 1.5 Ω
Short-Circuit Current Measured with VDAC shorted to
ground and to associated power
supply
VDAC0 and VDAC1 ±200 mA
VDAC2 and VDAC3 ±170 mA
VDAC4 and VDAC5 ±200 mA
VDAC6 and VDAC7 ±200 mA
VDAC Outputs Capacitive load up to 0.01 µF
Output Impedance
VDAC0, VDAC1, and VDAC4
to VDAC7
1.8 Ω
1.2
Ω
Output Range Buffer on
VDAC0 and VDAC1 0.15 AV
DD
–
600 mV
V R
L
= 75 Ω, 40 mA maximum, V
OUT
maximum = 3 V
VDAC2 and VDAC3 AV
NEG
+
250 mV
−0.15 V R
L
= 500 Ω, 10 mA maximum, V
OUT
maximum = −5 V, gain = −2.25 V
VDAC4 and VDAC5 0.15 AV
DD
–
300 mV
V R
L
= 300 Ω, 10 mA maximum, V
OUT
maximum = 3 V
VDAC6 0.15 VDACV
DD
−
250 mV
V R
L
= 500 Ω, 10 mA maximum, V
OUT
maximum = 5 V
VDAC7 0.15 VDACV
DD
−
700 mV
V R
L
= 100 Ω, 50 mA maximum, V
OUT
maximum = 5 V
DAC AC CHARACTERISTICS
Slew Rate
VDAC0, VDAC1, VDAC4, and
VDAC5
3 V/µs
VDAC2, VDAC3, and VDAC6 1.1 V/µs
Voltage Output Settling Time 10 µs Load =100 pF
0.05 ms Load = 0.01 µF
Digital-to-Analog Glitch Energy 20 nV/sec 1 LSB change at major carry
(DACxDAT register change from
0x07FF0000 to 0x08000000)
AC PSRR 100 Hz
VDAC0, VDAC1, VDAC4, and
VDAC5
72 dB
VDAC2 and VDAC3 67 dB
64
dB
AC PSRR 1 kHz
VDAC0, VDAC1, VDAC4, and
VDAC5
56 dB
VDAC2 and VDAC3 53 dB
VDAC6 and VDAC7 50 dB
POWER-ON RESET (POR) Refers to voltage at DVDD pin
POR Trip Level 2.81 2.85 2.9 V Power-on level
2.74 2.79 2.83 V Power-down level
POR Hysteresis 65 mV
ADuCM310 Data Sheet
Rev. A Page 10 of 27
Parameter Min Typ Max Unit Test Conditions/Comments
EXTERNAL RESET
External Reset Minimum Pulse
Width
1
1.5 µs Minimum pulse width required on
external
RESET
pin to trigger a
reset sequence
Reset Pin Glitch Immunity
1
50 ns Maximum low pulse width on
RESET
pin that does not generate a reset
Accuracy
1
1.25 1.37 1.494 V Indicates die temperature; ADC
measured voltage for temperature
sensor channel without calibration,
T
A
= 25°C
FLASH/EE MEMORY
Endurance 10,000 Cycles
Data Retention 20 Years T
J
= 85°C
INTERNAL HIGH POWER OSCILLATOR 16 MHz Used as input to PLL to generate
80 MHz clock
Accuracy −2.25 +2.25 %
INTERNAL LOW POWER OSCILLATOR 32.768 kHz
Accuracy −12 ±8 +12 %
LOGIC INPUTS
Input Low Voltage (V
) 0.2 × IOV
DD
V
Input High Voltage (V
) 0.7 × IOV
DD
V
Short-Circuit Current
1
12 mA
LOGIC OUTPUTS
Output High Voltage (V
)
10
IOV
DD
− 0.4 V I
SOURCE
= 2 mA
Output Low Voltage (V
)
10
0.4 V I
SINK
= 2 mA
Short-Circuit Current
1
12 mA
INPUT LEAKAGE CURRENT
Logic 1 80 µA V
INH
= 3.6 V
Internal Pull-Up Disabled −20 +6 +20 nA
Logic 0 80 µA V
INH
= 0 V
Internal Pull-Up Disabled −20 +6 +20 nA
Pull-Up 30 40 65 kΩ If not disabled, disabled at reset;
pull-up can be described as an
80 µA (typical) current source
CRYSTAL INPUTS XCLKI AND XCLKO
(16 MHz)
Logic Inputs, XCLKI Only
Input Low Voltage (V
) 1.1 V
Input High Voltage (V
) 1.7 V
XCLKI Input Capacitance 8 pF
XCLKO Output Capacitance 8 pF
MICROCONTROLLER UNIT CLOCK RATE
Using PLL Output
1
0.05 80 MHz
PROCESSOR START-UP TIME
At Power-On
38 50 ms Includes kernel power-on
execution time
After Reset Event 1.44 ms Includes kernel power-on
execution time
Mode 1, Mode 2, or Mode 3 3 to 5 f
CLK
Data Sheet ADuCM310
Rev. A Page 11 of 27
Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS
Power Supply Voltage Range
AV
DD
2.9 3.3 3.6 V Measured between AVDDx and
AGND
IOV
DD
2.9 3.3 3.6 V Measured between IOVDDx
and
AGND
Analog Power Supply Currents
AV
Current 6.5 7.2 mA ADC, VDACs, IDACs off
Digital Power Supply Current
Current in Normal Mode
DV
29 32 mA CLKCON1[2:0] = [000b]
IOV
2.7 3.1 mA All GPIO pull-ups enabled
Additional Power Supply Currents
ADC
1
3.1 3.6 mA ADC continuously converting at
100 kSPS
ADC Input Buffer
1
4.1 4.8 mA Both buffers enabled
IDAC
26.5 30 mA
DAC
2.7 3.1 mA Total for all VDACs driving
maximum allowed load with
DACxDAT = 0
VDAC2 and VDAC3
1
−1.7 mA I
DD
when VDAC2 and VDAC3 are
driving maximum allowed load
with DACxDAT set to 0
VDAC6 and VDAC7
1 mA I
DD
sourced from the VDACV
DD
supply when VDAC6 and VDAC7
are driving the maximum allowed
load with DACxDAT set to 0
1
These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
2
The input current is the total input current including the input pad and mux leakage plus the charge current for the full input circuit. The input current relates to the
ADC sampling frequency.
3
The internal reference calibration and trimming are performed when the processor operates in normal mode with CD = 0, when ADC is enabled and converting, when
IDACs are all on, and when VDACs are on. V
REF
accuracy can vary under other operating conditions.
4
Measured using the following box method:
( )
( )
( )
6
1
2.5
×
−×
−
Minimume
TemperaturMaximume
Temperatur
eTemperatur
AnyatMinimum
V
eTemperaturAny
atMaximumV
REFREF
5
VDAC linearity specifications are calculated with following ranges:
VDAC0 and VDAC1 = +150 mV to +2.699 V
VDAC2 and VDAC3: −150 mV to −4.22 V
VDAC4 and VDAC5: +150 mV to +2.98 V
VDAC6: +150 mV to +4.747 V
VDAC7: +150 mV to +4.297 V
6
Analog Devices, Inc., production IDAC full-scale trimming conditions include PVDD_IDACx pin voltage = 0.7 V, all IDACs on.
7
The long-term stability specifications is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
8
For all VDAC specifications for VDAC0, VDAC1, VDAC4, and VDAC5, DACxCON[10:9] = 11.
9
VDACx minimum and maximum limits apply to the internal reference only (DACxCON[1:0] = 00
b
). AVDDx supply valid only with typical specifications.
10
The average current from the GPIO pins must not exceed 3 mA per pin. See Figure 22.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

ADUCM310BBCZ-RL

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Buy ADUCM310BBCZ-RL
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz M3 wi 14Bit Analog for TSFP+ (Fin)
Lifecycle:
New from this manufacturer.
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