Data Sheet ADuCM310
Rev. A Page 3 of 27
GENERAL DESCRIPTION
The ADuCM310 is a multidie stack, on-chip system designed
for diagnostic control of tunable laser optical module applications.
The ADuCM310 features a 16-bit (14-bit accurate) multichannel
successive approximation register (SAR) ADC, an ARM
Cortex™-M3 processor, eight voltage DACs (VDACs), six
current output DACs, and Flash/EE memory packaged in a
6 mm × 6 mm, 112-ball CSP_BGA package.
The bottom die in the stack supports the bulk of the low voltage
analog circuitry and is the largest of the three die. It contains
the ADC, VDACs, main IDAC circuits, as well as other analog
support circuits, such as the low drift precision 2.5 V voltage
reference source.
The middle die in the stack supports the bulk of the digital
circuitry, including the ARM Cortex-M3 processor, the flash
and SRAM blocks, and all of the digital communication
peripherals. In addition, this die provides the clock sources for
the whole chip. A 16 MHz internal oscillator is the source of the
internal PLL that outputs an 80 MHz system clock.
The top die, which is the smallest die, was developed on a high
voltage process, and this die supports the 5 V and +5 V VDAC
outputs. It also implements the SOA IDAC current sink circuit
that allows the external SOA diode to pull to a −3.0 V level to
implement the fast shutdown of the laser output.
Regarding the individual blocks, the ADC is capable of
operating at conversion rates up to 800 kSPS. There are
10 external inputs to the ADC, which can be single ended or
differential. Several internal channels are included, such as the
supply monitor channels, an on-chip temperature sensor, and
internal voltage reference monitors.
The VDACs are 12-bit string DACs with output buffers capable
of sourcing between 10 mA and 50 mA, and these DACs are all
capable of driving 10 nF capacitive loads.
The low drift current DACs have 14-bit resolution and varied
full-scale output ranges from 0 mA to 20 mA to 0 mA to
250 mA on the SOA IDAC (IDAC3). The SOA IDAC also
comes with a 0 mA to −80 mA current sink capability.
A precision 2.5 V on-chip reference source is available. The internal
ADC, IDACs, and VDAC circuits use this on-chip reference
source to ensure low drift performance for all of these peripherals
The ADuCM310 also provides 2× buffered reference outputs
capable of sourcing up to 1.2 mA. These outputs can be used
externally to the chip.
The ADuCM310 integrates an 80 MHz ARM Cortex-M3
processor. It is a 32-bit reduced instruction set computer (RISC)
machine, offering up to 100 DMIPS peak performance. The ARM
Cortex-M3 processor also has a flexible 14-channel direct
memory access (DMA) controller supporting serial peripheral
interface (SPI), UART, and I
2
C communication peripherals. The
ADuCM310 has 256 kB of nonvolatile Flash/EE memory and
32 kB of SRAM integrated on-chip.
A 16 MHz on-chip oscillator generates the 80 MHz system
clock. This clock internally divides to allow the processor to
operate at lower frequency, thus saving power. A low power
internal 32 kHz oscillator is available and can clock the timers.
The ADuCM310 includes three general-purpose timers, a
wake-up timer (which can be used as a general-purpose timer),
and a system watchdog timer.
A range of communication peripherals can be configured as
required in a specific application. These peripherals include
UA RT, 2 × I
2
C, 2 × SPI, GPIO ports, and pulse-width
modulation (PWM).
On-chip factory firmware supports in-circuit serial download via
the UART, while nonintrusive emulation and program download
are supported via the serial wire debug port (SW-DP) interface.
These features are supported on the EVA L-ADuCM310QSPZ
development system.
The ADuCM310 operates from 2.9 V to 3.6 V and is specified
over a temperature range of 10°C to +85°C.
Note that, throughout this data sheet, multifunction pins, such
as P1.0/SIN/ECLKIN/PLAI[4], are referred to either by the
entire pin name or by a single function of the pin, for example,
P1.0, when only that function is relevant.
For additional information on the ADuCM310, see the
ADuCM310 reference manual, How to Set Up and Use the
ADuCM310.
ADuCM310 Data Sheet
Rev. A Page 4 of 27
SPECIFICATIONS
AV
DD
= IOV
DD
= DV
DD
= 2.9 V to 3.6 V (the input supply voltages). The difference between AV
DD
, IOV
DD
, and DV
DD
must be 0.3 V.
AV
NEG
(the supply voltage) = −5.5 V to 4.65 V. VDACV
DD
(the VDAC supply voltage) = 3.07 V to 5.35 V (for VDAC6 and VDAC7),
and VDACV
DD
must be AV
DD
. PV
DD
(the IDAC supply voltage) for the IDACs = 1.8 V to 2.7 V. AV
DD
≥ PV
DD
+ 0.4V. V
REF
= 2.5 V
internal reference, f
CORE
= 80 MHz, T
A
= 10°C to +85°C, unless otherwise noted.
For power sequencing, apply power to the AV
NEG
or VDACV
DD
pin before connecting the ground pins.
For register and bit information, see the ADuCM310 reference manual, How to Set Up and Use the ADuCM310.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
ADC CHANNEL SPECIFICATIONS All measurements in single-ended
mode, unless otherwise stated
ADC Power-Up Time 5 µs f
SAMPLE
≥500 kSPS
DC Accuracy
Resolution 14 Bits
Integral Nonlinearity
Input Buffer
±1.5
LSB
2.5 V internal reference
Enabled ±2.5 LSB
Disabled ±1.5 LSB External reference
Differential Nonlinearity 0.99 ±0.7 +1.5 LSB 2.5 V internal reference;
no missing codes
−0.99 ±0.7 +1.5
1
LSB 2.5 V external reference;
no missing codes
DC Code Distribution ±3 LSB ADC input voltage = 1.25 V dc
ENDPOINT ERRORS
Offset Error (All Channels Except
the Internal Channels)
ADC update rate up to 800 kSPS
Buffer On or Buffer Off 0.6 ±0.2 +0.6 mV Buffer on, chop mode on and
automatic zero or buffer off
Offset Error Drift
1
Buffer On or Buffer Off ±2.5 µV/°C Buffer on, chop mode on and
automatic zero or buffer off
Full-Scale Error
ADC update rate up to 800 kSPS
Buffer On or Buffer Off 0.7 ±0.2 +0.6 mV Excluding internal channels
Internal Channels ±0.2 +0.6 % of full scale Input buffer on; AV
DD
/2, IOV
DD
/2,
PV
DD
voltage on PVDD_IDAC2 pin
0.75 1.5 % of full scale Input buffer on; IDAC0 to IDAC5;
measured with 1.5 V on the IDAC0
to IDAC5 pins
Gain Error Drift
1
2 µV/°C Full-scale error drift minus offset
error drift; all modes; internal
reference
DYNAMIC PERFORMANCE
1
f
IN
= 665.283 Hz sine wave; f
SAMPLE
=
100 kSPS; internally unbuffered
channels; the filter on the analog
inputs is a 15 resistor and a 2 nF
capacitor
Signal-to-Noise Ratio (SNR)
Input Buffer
Disabled 80 dB Includes distortion and noise
components
Enabled 78 dB Chop mode on
74 dB Automatic zero
Data Sheet ADuCM310
Rev. A Page 5 of 27
Parameter Min Typ Max Unit Test Conditions/Comments
Total Harmonic Distortion (THD)
Input Buffer
Disabled 86 dB
Enabled 86 dB Chop mode on and automatic zero
88
dB
Buffer on and off
Channel-to-Channel Crosstalk 95 dB Measured on adjacent channels; f
IN
=
25 kHz sine wave; buffer on and off
Absolute Input Voltage Range
Unbuffered Mode AGND AV
DD
V Voltage level on AINx pin
Buffered Mode AGND + 0.15 2.5 V Voltage level on AINx pin
Input Voltage Ranges
Differential Mode −V
REF
+V
REF
V Voltage difference between AIN+
(positive input) and AIN− (negative
input)
Common-Mode Voltage Range 0.9 1.6 V
Single-Ended Mode AGND V
REF
V Voltage difference between AIN+
and AIN
Input Current
2
Buffered Mode V
IN
= 0.15 V to 2.5 V
AIN0, AIN1, AIN2, and AIN3 10
1
±5 +12.5
1
nA ADC sampling rate ≤ 100 kSPS
40 ±15 +60 nA ADC sampling rate ≤ 500 kSPS
60
1
±25 +90
1
nA ADC sampling rate ≤ 800 kSPS
Input Current Drift ±10 pA/°C Input buffer on, ADC sampling rate ≤
500 kSPS
±20 pA/°C Input buffer on, ADC sampling rate ≤
800 kSPS
AIN4 to AIN9 50
1
±20 +50
1
nA AIN4 to AIN9 ≤ 100 kSPS
210
1
±50 +110
1
nA ADC sampling rate ≤ 500 kSPS
350
1
90 +90
1
nA ADC sampling rate ≤ 800 kSPS
Unbuffered Mode 1100
1
+750 +1700
1
nA V
IN
= 0 V to 2.5 V, all channels, all
sampling rates
Input Current Drift ±140 pA/°C V
IN
= 1 V
Input Capacitance 20 pF During ADC acquisition, buffer on
Input Leakage Current 1.6
1
+1 +3.5
1
nA ADC off, buffer off or buffer on,
AINx connected 2.5 V
ON-CHIP VOLTAGE REFERENCE 0.47 µF from VREF_1.2 to AGND
Output Voltage 2.505 V
Accuracy
±5 mV T
A
= 25°C
Reference Temperature Coefficient
15 30 ppm/°C
Power Supply Rejection Ratio 70 dB
Output Impedance 3 For ADC_CAPP, T
A
= 25°C
Internal V
Power-On Time
1
38 50 ms Turned on by default
EXTERNAL REFERENCE INPUT
Input Voltage Range
1
1.8 2.5 V ADC maximum reference voltage =
2.5 V
External to Internal Reference 2.5
ms
Internal to External Reference 1
ms

ADUCM310BBCZ-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz M3 wi 14Bit Analog for TSFP+ (Fin)
Lifecycle:
New from this manufacturer.
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