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ADUCM310BBCZ-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
ADuCM310 Data Sheet
Rev. A Page 18 of 27
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESERVED IDAC0 PVDD_
IDAC0
IDAC2 PVDD_
IDAC2
IDAC3 PGND PVDD_
IDAC3
PVDD_
IDAC1
IDAC1 RESERVED
1 2 3 4 5 6 7 8 9 10 11
1 2 3 4 5 6 7 8 9 10 11
IDAC4 CDAMP_
IDAC0
CDAMP_
IDAC2
IDAC2 PVDD_
IDAC2
IDAC3 PGND PVDD_
IDAC3
CDAMP_
IDAC3
CDAMP_
IDAC1
IDAC5
PVDD_
IDAC4
CDAMP_
IDAC4
P2.3/BM
P1.0/
SIN/
ECLKIN/
PLAI[4]
P1.2/
PWM0/
PLAI[6]
P1.3/
PWM1/
PLAI[7]
P1.4/
PWM2/
SCLK1/
PLAO[10]
P1.5/
PWM3/
MISO1/
PLAO[11]
P1.6/
PWM4/
MOSI1/
PLAO[12]
CDAMP_
IDAC5
PVDD_
IDAC5
RESERVED RESET
P3.2/
PLAI[14]
P2.0/IRQ2/
PWMTRIP/
PLACLK2/
PLAI[8]
P1.1/SOUT/
PLACLK1/
PLAI[5]
RESERVED
P2.4/IRQ5/
ADCCONV/
PWM6/
PLAO[18]
P2.5/IRQ6/
PWM7/
PLAO[19]
P1.7/IRQ1/
PWM5/CS1/
PLAO[13]
DGND2 IREF
IOVDD1
P0.1/
MISO0/
PLAI[1]
P0.0/
SCLK0/
PLAI[0]
P2.2/IRQ4/
MRST/
CLKOUT/
PLAI[10]
P2.1/IRQ3/
PWMSYNC/
PLAI[9]
SWDIO SWCLK IOVDD2
IOGND1
P0.3/
IRQ0/CS0/
PLAI[3]
P0.2/
MOSI0/
PLAI[2]
RESERVED
ADuCM310
TOP VIEW
(Not to Scale)
RESERVED VDACV
DD
AVDD_REG1 IOGND2
P0.7/
SDA1/
PLAO[5]
P0.6/
SCL1/
PLAO[4]
P0.5/
SDA0/
PLAO[3]
P.04/
SCL0/
PLAO[2]
AIN4
AGND2 AVDD_REG2 VREF_1.2
P2.6/
IRQ7/
PLAO[20]
P2.7/
IRQ8/
PLAO[21]
P3.0/
PLAI[12]
AGND5 VDAC5 RESERVED AIN1 AIN5 VDAC6 VDAC7 AVDD4
P3.4/
PLAO[26]
XTALO P3.1/
PLAI[13]
VDAC4 DVDD AIN0 AIN2 AIN6 VDAC2 BUF_
VREF2.5A
AGND4
IOVDD3 XTALI DVDD_REG1 VDAC1 AGND1 AV
NEG
AIN3 AIN7 VDAC3 ADC_CAPN BUF_
VREF2.5B
IOGND3
A
B
C
D
E
F
G
H
J
K
L
IDAC RELATED DIGITAL PINS ANALOG PINS RESERVED
A
B
C
D
E
F
G
H
J
K
L
DGND1 DVDD_REG2 VDAC0 AVDD3 AGND3 AGND6
AIN8 AIN9 ADC_CAPN ADC_CAPP
13040-007
Figure 7. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Type
1
Description
D2
RESET
I Reset Input (Active Low). An internal pull-up is included on this pin.
E3
P0.0/SCLK0/PLAI[0]
I/O
General-Purpose Input and Output Port 0.0/SPI0 Clock/Input to PLA
Element 0. This pin defaults as an input with the internal pull-up resistor
disabled.
E2 P0.1/MISO0/PLAI[1] I/O General-Purpose Input and Output Port 0.1/SPI0 Data Master Input-Slave
Output/Input to PLA Element 1. This pin defaults as an input with the
internal pull-up disabled.
F3 P0.2/MOSI0/PLAI[2] I/O General-Purpose Input and Output Port 0.2/SPI0 Data Master Output-
Slave Input/Input of PLA Element 2. This pin defaults as an input with the
internal pull-up disabled.
F2 P0.3/IRQ0/
CS0
/PLAI[3] I/O General-Purpose Input and Output Port 0.3/External Interrupt Request 0/
SPI0 Chip Select Input/Input of PLA Element 3. This pin defaults as an
input with the internal pull-up disabled. If SPI0 is used, configure this pin
as
CS0
.
G4 P0.4/SCL0/PLAO[2] I/O General-Purpose Input and Output Port 0.4/I
2
C Interface Clock for
I2C0/Output of PLA Element 2. This pin defaults as an input with the
internal pull-up disabled.
Data Sheet ADuCM310
Rev. A Page 19 of 27
Pin No. Mnemonic Type
1
Description
G3 P0.5/SDA0/PLAO[3] I/O General-Purpose Input and Output Port 0.5/I
2
C Interface Data for
I2C0/Output of PLA Element 3. This pin defaults as an input with internal
pull-up disabled.
G2 P0.6/SCL1/PLAO[4] I/O General-Purpose Input and Output Port 0.6/I
2
C Interface Clock for
I2C1/Output of PLA Element 4. This pin defaults as an input with internal
pull-up disabled.
G1 P0.7/SDA1/PLAO[5] I/O General-Purpose Input and Output Port 0.7/I
2
C Interface Data for
I2C1/Output of PLA Element 5. This pin defaults as an input with internal
pull-up disabled.
C4 P1.0/SIN/ECLKIN/PLAI[4] I/O General-Purpose Input and Output Port 1.0/UART Input Pin/External
Input Clock/Input to PLA Element 4. The ECLKIN pin is used for the UART
downloader. This pin defaults as an input with internal pull-up disabled.
D5 P1.1/SOUT/PLACLK1/PLAI[5] I/O General-Purpose Input and Output Port 1.1/UART Output Pin/PLA Input
Clock/Input to PLA Element 5. The PLACLK1 pin is used for the UART
downloader. This pin defaults as an input with internal pull-up disabled.
C5 P1.2/PWM0/PLAI[6] I/O General-Purpose Input and Output Port 1.2/PWM0 Output/Input to PLA
Element 6. This pin defaults as an input with internal pull-up disabled.
C6 P1.3/PWM1/PLAI[7] I/O General-Purpose Input and Output Port 1.3/PWM1 Output/Input to PLA
Element 7. This pin defaults as an input with internal pull-up disabled.
C7 P1.4/PWM2/SCLK1/PLAO[10] I/O General-Purpose Input and Output Port 1.4/PWM2 Output/SPI1
Clock/Output of PLA Element 10. This pin defaults as an input with
internal pull-up disabled.
C8 P1.5/PWM3/MISO1/PLAO[11] I/O General-Purpose Input and Output Port 1.5/PWM3 Output/SPI1 Data
Master Input-Slave Output/Output of PLA Element 11. This pin defaults as
an input with internal pull-up disabled.
C9 P1.6/PWM4/MOSI1/PLAO[12] I/O General-Purpose Input and Output Port 1.6/PWM4 Output/SPI1 Data
Master Output-Slave Input/Output of PLA Element 12. This pin defaults as
an input with internal pull-up disabled.
D9 P1.7/IRQ1/PWM5/
CS1
/PLAO[13] I/O General-Purpose Input and Output Port 1.7/External Interrupt Request 1/
PWM5 Output/SPI1 Chip Select Input/Output of PLA Element 13. This pin
defaults as an input with internal pull-up disabled. If SPI1 is used,
configure this pin as
CS1
.
D4
P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8]
I/O
General-Purpose Input and Output Port 2.0/External Interrupt Request 2/
PWM Trip Input Source/PLA Input Clock/Input to PLA Element 8. This pin
defaults as an input with the internal pull-up disabled.
E8 P2.1/IRQ3/PWMSYNC/PLAI[9] I/O General-Purpose Input and Output Port 2.1/External Interrupt Request 3/
PWM Sync Input/Input to PLA Element 9. This pin defaults as an input
with the internal pull-up disabled.
E4
P2.2/IRQ4/
MRST
/CLKOUT/PLAI[10]
I/O
General-Purpose Input and Output Port 2.2/External Interrupt Request 4/
Reset Out Pin/Clock Output/Input to PLA Element 10. This pin defaults as
an input with the internal pull-up disabled.
C3 P2.3/BM I/O General-Purpose Input and Output Port 2.3/BM pin. If this pin is low, then
the device enters UART download after the next rest sequence. This pin
defaults as an input with the internal pull-up disabled.
D7 P2.4/IRQ5/ADCCONV/PWM6/PLAO[18] I/O General-Purpose Input and Output Port 2.4/External Interrupt Request 5/
External Input to Start ADC Conversions/PWM6 Output/Output of
PLA Element 18. This pin defaults as an input with the internal pull-up
disabled.
D8 P2.5/IRQ6/PWM7/PLAO[19] I/O General-Purpose Input and Output Port 2.5/External Interrupt Request 6/
PWM7 Output/Output of PLA Element 19. This pin defaults as an input
with the internal pull-up disabled.
H1 P2.6/IRQ7/PLAO[20] I/O General-Purpose Input and Output Port 2.6/External Interrupt Request 7/
Output of PLA Element 20. This pin defaults as an input with the internal
pull-up disabled.
H2 P2.7/IRQ8/PLAO[21] I/O General-Purpose Input and Output Port 2.7/External Interrupt Request 8/
Output of PLA Element 21. This pin defaults as an input with the internal
pull-up disabled.
H3 P3.0/PLAI[12] I/O General-Purpose Input and Output Port 3.0/Input to PLA Element 12. This
pin defaults as an input with the internal pull-up disabled.
ADuCM310 Data Sheet
Rev. A Page 20 of 27
Pin No. Mnemonic Type
1
Description
J3 P3.1/PLAI[13] I/O General-Purpose Input and Output Port 3.1/Input to PLA Element 13. This
pin defaults as an input with the internal pull-up disabled.
D3 P3.2/PLAI[14] I/O General-Purpose Input and Output Port 3.2/Input to PLA Element 14. This
pin defaults as an input with the internal pull-up disabled.
J1
P3.4/PLAO[26]
I/O
General-Purpose Input and Output Port 3.4/Output of PLA Element 26. This
pin defaults as an input with the internal pull-up disabled.
E10 SWCLK I Serial Wire Debug Clock Input Pin.
E9 SWDIO I/O Serial Wire Debug Data Input/Output Input Pin.
G11 VREF_1.2 AO 1.2 V Reference Output. This pin cannot be used to source current
externally. Connect this pin to AGND via a 470 nF capacitor.
D11
IREF
AI
This pin generates the reference current for the IDACs. Connect this pin to
analog ground via a 5 ppm, 3.16 kΩ external resistor (R
EXT
).
J6 AIN0 AI Single-Ended or Differential Analog Input 0.
H7 AIN1 AI Single-Ended or Differential Analog Input 1.
J7 AIN2 AI Single-Ended or Differential Analog Input 2.
K7 AIN3 AI Single-Ended or Differential Analog Input 3.
G8 AIN4 AI Single-Ended or Differential Analog Input 4. This is also the input for the
digital comparator.
H8 AIN5 AI Single-Ended or Differential Analog Input 5.
J8 AIN6 AI Single-Ended or Differential Analog Input 6.
K8
AIN7
AI
Single-Ended or Differential Analog Input 7.
L8 AIN8 AI Single-Ended or Differential Analog Input 8.
L9 AIN9 AI Single-Ended or Differential Analog Input 9.
L4 VDAC0 AO 12-Bit VDAC Output 0, 0 V to 3 V Range.
K4 VDAC1 AO 12-Bit VDAC Output 1, 0 V to 3 V Range.
J9 VDAC2 AO 12-Bit VDAC Output 2, −5 V to 0 V Range.
K9 VDAC3 AO 12-Bit VDAC Output 3, −5 V to 0 V Range.
J4 VDAC4 AO 12-Bit VDAC Output 4, 0 V to 3 V Range.
H5 VDAC5 AO 12-Bit VDAC Output 5, 0 V to 3 V Range.
H9 VDAC6 AO 12-Bit VDAC Output 6, 0 V to 5 V Range.
H10 VDAC7 AO 12-Bit VDAC Output 7, 0 V to 5 V Range.
A2 IDAC0 AO IDAC0 (100 mA).
A3
PVDD_IDAC0
S
Power for IDAC0.
B2 CDAMP_IDAC0 AI Damping Capacitor Pin for IDAC0. Connect this pin to the PVDD supply.
A10 IDAC1 AO IDAC1 (100 mA).
A9 PVDD_IDAC1 S Power for IDAC1.
B10 CDAMP_IDAC1 AI Damping capacitor pin for IDAC1. Connect this pin to the PVDD supply.
B11 IDAC5 AO IDAC5 (20 mA).
C11 PVDD_IDAC5 S Power for IDAC5.
C10 CDAMP_IDAC5 AI Damping capacitor pin for IDAC5. Connect this pin to the PVDD supply.
B1 IDAC4 AO IDAC4 (20 mA).
C1 PVDD_IDAC4 S Power for IDAC4.
C2 CDAMP_IDAC4 AI Damping capacitor pin for IDAC4. Connect this pin to the PVDD supply.
A4, B4 IDAC2 AO IDAC2 (200 mA).
A5, B5 PVDD_IDAC2 S Power for IDAC2.
B3 CDAMP_IDAC2 AI Damping Capacitor for IDAC2. Connect this pin to the PVDD supply.
A6, B6 IDAC3 AO IDAC3 (250 mA).
A8, B8 PVDD_IDAC3 S Power for IDAC3.
B9 CDAMP_IDAC3 AI Damping Capacitor Pin for IDAC3. Connect this pin to the PVDD supply.
A7, B7
PGND
S
Power Supply Ground of the IDACs.
K5, G9,
L6, J11,
H4, L7
AGND1, AGND2, AGND3, AGND4,
AGND5, AGND6
S Analog Ground Pins.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

ADUCM310BBCZ-RL

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Buy ADUCM310BBCZ-RL
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz M3 wi 14Bit Analog for TSFP+ (Fin)
Lifecycle:
New from this manufacturer.
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