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LPC2210FBD144/01,5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 22 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
6.8 Pin function select register 2 (PINSEL2 - 0xE002 C014)
The PINSEL2 register controls the functions of the pins as per the settings listed in
Table 9. The direction control bit in the IODIR register is effective only when the GPIO
function is selected for a pin. For other functions direction is controlled automatically.
Settings other than those shown in Table 9 are reserved, and should not be used.
Table 9. Pin function select register 2 (PINSEL2 - 0xE002 C014)
PINSEL2 bits Description Reset value
1:0 reserved -
2 When 0, pins P1[36:26] are used as GPIO pins. When 1, P1[31:26] are used as a
Debug port.
P1.26/RTCK
3 When 0, pins P1[25:16] are used as GPIO pins. When 1, P1[25:16] are used as a
Trace port.
P1.20/
TRACESYNC
5:4 Controls the use of the data bus and strobe pins: BOOT1:0
Pins P2[7:0] 11 = P2[7:0] 0x or 10 = D7 to D0
Pin P1.0 11 = P1.0 0x or 10 =
CS0
Pin P1.1 11 = P1.1 0x or 10 =
OE
Pin P3.31 11 = P3.31 0x or 10 =
BLS0
Pins P2[15:8] 00 or 11 = P2[15:8] 01 or 10 = D15 to D8
Pin P3.30 00 or 11 = P3.30 01 or 10 =
BLS1
Pins P2[27:16] 0x or 11 = P2[27:16] 10 = D27 to D16
Pins P2[29:28] 0x or 11 = P2[29:28] 10 = D29, D28
Pins P2[31:30] 0x or 11 = P2[31:30] or AIN5 to
AIN4
10 = D31, D30
Pins P3[29:28] 0x or 11 = P3[29:28] or AIN7 to
AIN6
10 =
BLS2, BLS3
6 If bits 5:4 are not 10, controls the use of pin P3.29: 0 enables P3.29, 1 enables
AIN6.
1
7 If bits 5:4 are not 10, controls the use of pin P3.28: 0 enables P3.28, 1 enables
AIN7.
1
8 Controls the use of pin P3.27: 0 enables P3.27, 1 enables
WE. 0
10:9 reserved -
11 Controls the use of pin P3.26: 0 enables P3.26, 1 enables
CS1. 0
12 reserved -
13 If bits 27:25 are not 111, controls the use of pin P3.23/A23/XCLK: 0 enables P3.23,
1 enables XCLK.
0
15:14 Controls the use of pin P3.25: 00 enables P3.25, 01 enables
CS2, 10 and 11 are
reserved values.
00
17:16 Controls the use of pin P3.24: 00 enables P3.24, 01 enables
CS3, 10 and 11 are
reserved values.
00
19:18 reserved -
20 If bits 5:4 are not 10, controls the use of pin P2[29:28]: 0 enables P2[29:28], 1 is
reserved
0
21 If bits 5:4 are not 10, controls the use of pin P2.30: 0 enables P2.30, 1 enables
AIN4.
1
22 If bits 5:4 are not 10, controls the use of pin P2.31: 0 enables P2.31, 1 enables
AIN5.
1
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 23 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
6.9 External memory controller
The external static memory controller is a module which provides an interface between
the system bus and external (off-chip) memory devices. It provides support for up to four
independently configurable memory banks (16 MB each with byte lane enable control)
simultaneously. Each memory bank is capable of supporting SRAM, ROM, flash EPROM,
burst ROM memory, or some external I/O devices.
Each memory bank may be 8-bit, 16-bit, or 32-bit wide.
6.10 General purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
6.10.1 Features
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
6.11 10-bit ADC
The LPC2210/2220 each contain a single 10-bit successive approximation ADC with eight
multiplexed channels.
6.11.1 Features
• Measurement range of 0 V to 3 V.
• Capable of performing more than 400000 10-bit samples per second.
• Burst conversion mode for single or multiple inputs.
23 Controls whether P3.0/A0 is a port pin (0) or an address line (1). 1 if BOOT1:0 = 00
at
RESET = 0,
0 otherwise
24 Controls whether P3.1/A1 is a port pin (0) or an address line (1).
BOOT1 during
reset
27:25 Controls the number of pins among P3.23/A23/XCLK and P3[22:2]/A2[22:2] that
are address lines:
000 if
BOOT1:0 = 11 at
reset, 111
otherwise
000 = None 100 = A11 to A2 are address lines.
001 = A3 to A2 are address
lines.
101 = A15 to A2 are address lines.
010 = A5 to A2 are address
lines.
110 = A19 to A2 are address lines.
011 = A7 to A2 are address
lines.
111 = A23 to A2 are address lines.
31:28 reserved
Table 9. Pin function select register 2 (PINSEL2 - 0xE002 C014)
…continued
PINSEL2 bits Description Reset value
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 24 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
• Optional conversion on transition on input pin or Timer Match signal.
6.11.2 ADC features available in LPC2210/01 and LPC2220 only
• Every analog input has a dedicated result register to reduce interrupt overhead.
• Every analog input can generate an interrupt once the conversion is completed.
• The ADC pads are 5 V tolerant when configured for digital I/O function(s).
6.12 UARTs
The LPC2210/2220 each contain two UARTs. One UART provides a full modem control
handshake interface, the other provides only transmit and receive data lines.
6.12.1 Features
• 16 B receive and transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in baud rate generator.
• Standard modem interface signals included on UART1.
6.12.2 UART features available in LPC2210/01 and LPC2220 only
Compared to previous LPC2000 microcontrollers, UARTs in LPC2210/01 and LPC2220
introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers
to achieve standard baud rates such as 115200 Bd with any crystal frequency above
2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in
hardware.
• Fractional baud rate generator enables standard baud rates such as 115200 Bd to be
achieved with any crystal frequency above 2 MHz.
• Auto-bauding.
• Auto-CTS/RTS flow-control fully implemented in hardware.
6.13 I
2
C-bus serial I/O controller
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C-bus is a multi-master bus, and it
can be controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2210/2220 supports a bit rate up to 400 kbit/s (fast
I
2
C-bus).
6.13.1 Features
• Compliant with standard I
2
C-bus interface.
• Easy to configure as master, slave, or master/slave.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

LPC2210FBD144/01,5

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Buy LPC2210FBD144/01,5
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 16KR/10BADC ROMLESS
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