LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 39 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
[1] Except on initial access, in which case the address is set up T
cy(CCLK)
earlier.
[2] T
cy(CCLK)
=
1
⁄
CCLK
.
[3] Latest of address valid, CS LOW, OE LOW to data valid.
[4] See the
LPC2210/20 user manual UM10114_1
for a description of the WSTn bits.
[5] Address valid to data valid.
[6] Earliest of CS HIGH, OE HIGH, address change to data invalid.
t
BLSHDNV
BLS HIGH to data invalid
time
[2]
(2 × T
cy(CCLK)
) − 5 - (2 × T
cy(CCLK)
)+5 ns
t
CHDV
XCLK HIGH to data valid
time
- - 10 ns
t
CHWEL
XCLK HIGH to WE LOW time - - 10 ns
t
CHBLSL
XCLK HIGH to BLS LOW
time
- - 10 ns
t
CHWEH
XCLK HIGH to WE HIGH
time
- - 10 ns
t
CHBLSH
XCLK HIGH to BLS HIGH
time
- - 10 ns
t
CHDNV
XCLK HIGH to data invalid
time
- - 10 ns
Table 14. External memory interface dynamic characteristics
…continued
C
L
= 25 pF; T
amb
=40
°
C.
Symbol Parameter Conditions Min Typ Max Unit
Table 15. Standard read access specifications
Access cycle Max frequency WST setting
WST ≥ 0; round up to
integer
Memory access time requirement
standard read
standard write
burst read - initial
burst read - subsequent 3× N/A
MAX
2 WST1+
t
RAM
20 ns+
--------------------------------
≤
WST1
t
RAM
20 ns+
t
cy CCLK()
--------------------------------
≥ 2–
t
RAM
t
cy CCLK()
2 WST1+()× 20 ns–≤
MAX
1WST2+
t
WRITE
5ns+
----------------------------------
≤
WST2
t
WRITE
t
CYC
5+–
t
cy CCLK()
--------------------------------------------
≥
t
WRITE
t
cy CCLK()
1 WST2+()× 5ns–≤
MAX
2 WST1+
t
INIT
20 ns+
--------------------------------
≤
ST1
t
INIT
20 ns+
t
cy CCLK()
--------------------------------
≥ 2–
t
INIT
t
cy CCLK()
2 WST1+()× 20 ns–≤
MAX
1
t
ROM
20 ns+
---------------------------------
≤
t
ROM
t
cy CCLK()
20 ns–≤