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LPC2210FBD144/01,5

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 31 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
6.21.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol converter. EmbeddedICE protocol converter converts the remote
debug protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel (DCC) function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
The JTAG clock (TCK) must be slower than
1
⁄
6
of the CPU clock (CCLK) for the JTAG
interface to operate.
6.21.2 Embedded trace
Since the LPC2210/2220 have significant amounts of on-chip memory, it is not possible to
determine how the processor core is operating simply by observing the external pins. The
Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply
embedded processor cores. It outputs information about processor execution to the trace
port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
pipeline status on a cycle by cycle basis. Trace information generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed. Self-modifying code cannot be traced
because of this restriction.
6.21.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real-time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the debug
communication channel, which is present in the EmbeddedICE logic. The LPC2210/2220
contain a specific configuration of RealMonitor software programmed into the on-chip
flash memory.
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 32 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
7. Limiting values
[1] The following applies to Table 10:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless
otherwise noted.
[2] Internal rail.
[3] External rail.
[4] Including voltage on outputs in 3-state mode.
[5] Only valid when the V
DD(3V3)
supply voltage is present.
[6] Not to exceed 4.6 V.
[7] Per supply pin.
[8] The peak current is limited to 25 times the corresponding maximum current.
[9] Per ground pin.
[10] Dependent on package type.
[11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
Table 10. Limiting values reset
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Symbol Parameter Conditions Min Max Unit
V
DD(1V8)
supply voltage (1.8 V)
[2]
−0.5 +2.5 V
V
DD(3V3)
supply voltage (3.3 V)
[3]
−0.5 +3.6 V
V
DDA(3V3)
analog supply voltage (3.3 V) −0.5 +4.6 V
V
IA
analog input voltage −0.5 +5.1 V
V
I
input voltage 5 V tolerant I/O pins
[4][5]
−0.5 +6.0 V
other I/O pins
[4][6]
−0.5 V
DD(3V3)
+ 0.5 V
I
DD
supply current
[7][8]
- 100 mA
I
SS
ground current
[8][9]
- 100 mA
T
stg
storage temperature
[10]
−65 +150 °C
P
tot(pack)
total power dissipation (per
package)
based on package heat
transfer, notdevice power
consumption
- 1.5 W
V
esd
electrostatic discharge voltage human body model
[11]
all pins −2000 +2000 V
LPC2210_2220_6 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 06 — 11 December 2008 33 of 50
NXP Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers
8. Static characteristics
Table 11. Static characteristics
T
amb
=
−
40
°
C to +85
°
C for commercial applications, unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
V
DD(1V8)
supply voltage (1.8 V)
[2]
1.65 1.8 1.95 V
V
DD(3V3)
supply voltage (3.3 V)
[3]
3.0 3.3 3.6 V
V
DDA(3V3)
analog supply voltage
(3.3 V)
2.5 3.3 3.6 V
Standard port pins,
RESET, RTCK
I
IL
LOW-level input current V
I
= 0 V; no pull-up - - 3 µA
I
IH
HIGH-level input current V
I
=V
DD(3V3)
; no pull-down - - 3 µA
I
OZ
OFF-state output current V
O
=0V, V
O
=V
DD(3V3)
;
no pull-up/down
--3µA
I
latch
I/O latch-up current −(0.5V
DD(3V3)
) < V
I
<
(1.5V
DD(3V3)
); T
j
< 125 °C
100 - - mA
V
I
input voltage
[4][5][6]
0 - 5.5 V
V
O
output voltage output active 0 - V
DD(3V3)
V
V
IH
HIGH-level input voltage 2.0 - - V
V
IL
LOW-level input voltage - - 0.8 V
V
hys
hysteresis voltage 0.4 - - V
V
OH
HIGH-level output voltage I
OH
= −4 mA
[7]
V
DD(3V3)
−
0.4
--V
V
OL
LOW-level output voltage I
OL
= −4 mA
[7]
- - 0.4 V
I
OH
HIGH-level output current V
OH
=V
DD(3V3)
− 0.4 V
[7]
−4--mA
I
OL
LOW-level output current V
OL
= 0.4 V
[7]
4 --mA
I
OHS
HIGH-level short circuit
output current
V
OH
=0V
[8]
--−45 mA
I
OLS
LOW-level short circuit
output current
V
OL
=V
DD(3V3)
[8]
- - 50 mA
I
pd
pull-down current V
I
=5V
[9]
10 50 150 µA
I
pu
pull-up current V
I
=0V
[10]
−15 −50 −85 µA
V
DD(3V3)
< V
I
< 5 V
[9]
000µA
I
DD(act)
active mode supply current V
DD(1V8)
= 1.8 V;
T
amb
=25°C;
code
while(1){}
executed from on-chip
RAM; no active peripherals
CCLK = 60 MHz
(LPC2210)
- 5070mA
CCLK = 75 MHz
(LPC2210/01; LPC2220)
- 5070mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

LPC2210FBD144/01,5

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Buy LPC2210FBD144/01,5
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU ARM7 16KR/10BADC ROMLESS
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