©2004 Fairchild Semiconductor Corporation FDT461N Rev. A1
FDT461N
Figure 5. Forward Bias Safe Operating Area Figure 6. Transfer Characteristics
Figure 7. Saturation Characteristics Figure 8. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
Typical Characteristics T
A
= 25°C unless otherwise noted
0.01
0.1
1
110 120
4
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
J
= MAX RATED
T
A
= 25
o
C
SINGLE PULSE
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
100µs
1ms
10ms
0
0.4
0.8
1.2
1.6
1.5 2.0 2.5 3.0 3.5
I
D
, DRAIN CURRENT (A)
V
GS
, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
T
J
= 175
o
C
T
J
= 25
o
C
T
J
= -55
o
C
0
0.4
0.8
1.2
1.6
0 0.5 1.0 1.5 2.0 2.5 3.0
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 2.5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
A
= 25
o
C
V
GS
= 3V
V
GS
= 4.5V
1.0
1.5
2.0
2.5
3.0
2345678910
I
D
= 0.2A
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
= 0.54A
r
DS(ON)
, DRAIN TO SOURCE
ON RESISTANCE ()
PULSE DURATION = 80ms
DUTY CYCLE = 0.5% MAX
0.5
1.0
1.5
2.0
-80 -40 0 40 80 120 160
NORMALIZED DRAIN TO SOURCE
T
J
, JUNCTION TEMPERATURE (
o
C)
ON RESISTANCE
V
GS
= 10V, I
D
= 0.54A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 160
V
GS
= V
DS
, I
D
= 250µA
NORMALIZED GATE
T
J
, JUNCTION TEMPERATURE (
o
C)
THRESHOLD VOLTAGE
©2004 Fairchild Semiconductor Corporation FDT461N Rev. A1
FDT461N
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
Figure 13. Gate Charge Waveforms for Constant Gate Current
Typical Characteristics T
A
= 25°C unless otherwise noted
0.9
1.0
1.1
-80 -40 0 40 80 120 160
1.2
T
J
, JUNCTION TEMPERATURE (
o
C)
NORMALIZED DRAIN TO SOURCE
I
D
= 250µA
BREAKDOWN VOLTAGE
1
10
100
0.1 1 10 100
200
C, CAPACITANCE (pF)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
OSS
C
DS
+ C
GD
C
RSS
= C
GD
0
2
4
6
8
10
0 0.5 1.0 1.5 2.0 2.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
Q
g
, GATE CHARGE (nC)
V
DD
= 50V
I
D
= 0.54A
Test Circuits and Waveforms
Figure 14. Unclamped Energy Test Circuit Figure 15. Unclamped Energy Waveforms
t
P
V
GS
0.01
L
I
AS
+
-
V
DS
V
DD
R
G
DUT
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
0V
V
DD
V
DS
BV
DSS
t
P
I
AS
t
AV
0
©2004 Fairchild Semiconductor Corporation FDT461N Rev. A1
FDT461N
Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveforms
Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms
Test Circuits and Waveforms (Continued)
V
GS
+
-
V
DS
V
DD
DUT
I
g(REF)
L
V
DD
Q
g(TH)
V
GS
= 1V
Q
g(4.5)
V
GS
= 4.5V
Q
g(TOT)
V
GS
= 10V
V
DS
V
GS
I
g(REF)
0
0
Q
gs
Q
gd
V
GS
R
L
R
GS
DUT
+
-
V
DD
V
DS
V
GS
t
ON
t
d(ON)
t
r
90%
10%
V
DS
90%
10%
t
f
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
0
0

FDT461N

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
MOSFET NCH LOGIC ENHANCEMEN MODFIELD EFFECT TRAN
Lifecycle:
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