HTSICH56_48_SDS All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.1 — 11 December 2014
210331 15 of 21
NXP Semiconductors
HTSICH56; HTSICH48
HITAG S transponder IC
7.5.9 WRITE BLOCK
After transmitting the WRITE BLOCK command, the Page address PADR (8 Bits) within a
Block and the 8 bit Cyclic Redundancy Check (CRC 8), the HITAG S Transponder
responds with the SOF and an acknowledge (ACK) to confirm the reception of a correct
WRITE BLOCK command. After the waiting time t
wsc
the RWD transmits the write data
with CRC 8 Page by Page (1 to 4 Pages depending on the Page address PADR within the
corresponding block). After the programming time t
prog
the HITAG S Transponder
responds with a SOF and an acknowledge to confirm correct programming of each Page.
Table 14. Write block
MSB LSB MSB LSB
RWD: 1 0 0 1 PADR CRC 8 EOF t
wsc
ACK
Transponder: t
wresp
SOF 01
Table 15. Write data for page with page address: PADR
LSByte MSByte
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
RWD: DATA 0 DATA 1 DATA 2 DATA 3 CRC 8 EOF t
wsc
ACK
Transponder: t
prog
SOF 01
Table 16. Write data for page with page address: PADR + 1
LSByte MSByte
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
RWD: DATA 0 DATA 1 DATA 2 DATA 3 CRC 8 EOF t
wsc
ACK
Transponder: t
prog
SOF 01
Table 17. Write data for page with page address: PADR + 2
LSByte MSByte
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
RWD: DATA 0 DATA 1 DATA 2 DATA 3 CRC 8 EOF t
wsc
ACK
Transponder: t
prog
SOF 01
Table 18. Write data for page with page address: PADR + 3
LSByte MSByte
MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
RWD: DATA 0 DATA 1 DATA 2 DATA 3 CRC 8 EOF
ACK
Transponder: t
prog
SOF 01
