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72V295L10PFG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
19
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TM
131,072 x 18, 262,144 x 18
Figure 10. Read Timing (First Word Fall Through Mode)
NOTES:
1. t
SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1,
then the IR assertion may be delayed one extra WCLK cycle.
2. t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
t
SKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 131,073 for IDT72V295 and 262,145 for IDT72V2105.
WCLK
12
WEN
D
0
- D
17
RCLK
t
ENS
REN
Q
0
- Q
17
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
t
OHZ
t
SKEW1
(1)
t
ENH
t
DS
t
OE
t
A
t
A
t
A
t
PAF
t
WFF
t
WFF
t
ENS
OE
t
SKEW2
(2)
W
D
4668 drw 13
t
PAE
W
[D-n]
W
[D-n-1]
t
A
t
A
t
HF
][
W
][
W
t
REF
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
t
ENS
1
t
DH
20
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TM
131,072 x 18, 262,144 x 18
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 131,072 for IDT72V295 and 262,144 for IDT72V2105.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
Figure 11. Retransmit Timing (IDT Standard Mode)
t
REF
t
RTS
t
ENH
4668 drw 14
t
A
t
ENS
W
x
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q
0
- Q
n
t
SKEW2
12
1
W
1
(3)
t
PAF
t
HF
t
PAE
t
REF
W
x+1
2
W
2
(3)
t
ENH
WEN
t
ENS
t
RTS
t
ENS
t
ENH
t
A
t
A
21
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
TM
131,072 x 18, 262,144 x 18
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 131,073 for the IDT72V295 and 262,145 for the IDT72V2105.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
Figure 12. Retransmit Timing (FWFT Mode)
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. X = 16 for the IDT72V295 and X = 17 for the IDT72V2105.
tREF
tRTS
tENH
4668 drw 15
tENS
Wx
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
0 - Qn
tSKEW2
12
1
tPAF
tHF
tPAE
tREF
Wx+1
2
W2
(4)
tENH
tRTS
WEN
tENS
W1
(4)
tENS
3
4
tENH
W3
(4)
tAtA
tA
W4
tA
WCLK
SEN
SI
4668 drw 16
t
ENH
t
ENS
t
LDS
LD
t
DS
BIT 0
EMPTY OFFSET
BIT X
(1)
BIT 0
FULL OFFSET
t
ENH
BIT X
(1)
t
LDH
t
LDH
t
DH
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

72V295L10PFG

Mfr. #:
Buy 72V295L10PFG
Manufacturer:
IDT
Description:
FIFO 3.3V 4M SUPER SYNC II
Lifecycle:
New from this manufacturer.
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